12-Bit, 2GSPS Data Acquisition Reference Design

By interleaving Renesas' low power, high sample rate ADCs, it is possible to achieve a combination of ultra-high sample rate and very high dynamic range that is not available in today’s stand-alone ADCs.

This reference design demonstrates the performance attainable by combining Renesas' ADC technology and SP Devices' interleaving algorithms. In this design, four ISLA112P50 12-bit, 500MSPS analog-to-digital converters are interleaved to sample at a rate of 2.0GSPS. At this sampling rate, the reference design provides over 6dB more SNR and 13dB better SFDR than the best alternative stand-alone ADC.

Main features

• Collaboration of Renesas and SP Devices

• Demonstrates 4-way interleaving of Renesas 500MSPS ISLA112P50s

• Sample rate: 2.0GSPS

• Resolution: 12 bits

• Interleave correction details

• SP Devices’ ADX4 provides real-time, digital, FPGA based digital interleave correction of four ISLA112P50s' performance

• Performance

• SNR = 65.5dBfs @ Fin = 190MHz, a 6dB improvement over current best standalone 2GSPS ADCs
  

• SFDR = 82dBc @ Fin = 190MHz, a 13dB SFDR improvement over current best standalone 2GSPS ADCS
  

application

• Radar and electronic/signal intelligence

• Broadband communications

• High-performance data acquisition