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Why is there a small series resistor on the digital signal line? (DC2222A LTC2500) [Copy link]

 

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Hello Expert,

I looked at the schematic of the DC2222A (LTC2500 evaluation board) and found that all digital signal transmission lines (such as between the FPGA and the ADC) have a 33Ω series resistor (even the clock line), as shown below:

The digital circuit clock signal is about 50MHz, and the ADC data sheet specifically mentions the use of a low-jitter clock source.

Excuse me:

What is the function of this 33Ω resistor ? (My senior said it is used to prevent overshoot, but I think that considering that the Ci of the io receiving end is in the pF level, this function should be negligible)

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Signal integrity, which introduces the great influence of impedance matching on high-speed signals. You can refer to   Details Published on 2022-4-21 14:29
 

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This post was last edited by RobertLiang on 2022-5-12 11:30

Summary of the answer:

First of all, I would like to thank the forum experts for their answers, which gave me inspiration and guidance. However, these answers are still not specific enough.

Recently, I saw the official explanation in the Xilinx official document: <ug471_selectIO_Kintex_7_FPGA>. Therefore, the answer to this question is further expanded and supplemented as follows:

> Chp: Supported I/O Standards and Terminations

> LVCMOS (Low Voltage CMOS)

The figure above shows three recommended " matching methods " for LVCMOS (matching, that is, preventing the reflection of the signal waveform at the termination, so as to quickly achieve signal stability), from top to bottom:

1. No matching (the simplest way, most IOs in KC705 are also processed in this way, maybe Xilinx thinks that non-high-performance IO ports do not need matching processing);

2. Beginning match (I think this is the standard answer to this question);

Why is the series " damping resistor RS " selected as 33, 22Ω instead of the standard transmission line impedance 50Ω? Because the role of RS is to add to the output impedance RD of LVCMOS to achieve the purpose of matching with the transmission line Z0.

3. Terminal matching

A resistor is required to be pulled to the GND or power plane. The advantage is that the first reflection of the signal is suppressed and the SI performance is the best (doubtful, welcome to correct?). The disadvantage is that it is more complicated than the initial matching and has DC power consumption.

From now on the answer to my question is clear:

DC2222A uses "start-end matching"; the selection of matching resistor + output impedance of the output port = characteristic impedance of the transmission line; start-end matching can prevent secondary reflection when the signal returns to the output port, causing unstable phenomena such as ringing.


Further expansion, for bidirectional IO ports, it is only suitable for mismatch or terminal matching, not for start-end matching.


Finally, I would like to raise some detailed questions. If you are interested, please feel free to discuss:

1. I did not see the parameters of the output impedance of the output port in various Xilinx manuals. Is it recommended to select the value of the initial resistance only through testing?

2. Which matching method should I choose? Are there clearer standards and boundaries?

Thanks again!

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1w

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This resistor is necessary in high-speed digital circuits for impedance matching and suppressing signal reflection to ensure signal quality.

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Personal signature上传了一些书籍资料,也许有你想要的:http://download.eeworld.com.cn/user/chunyang
 
 
 

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In practice, you can use an oscilloscope to measure whether the signal line has a 22 ohm or 33 ohm eye diagram, which will help you better understand the role of the resistor.

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2w

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The main function of this series resistor is to suppress signal reflection.

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Damping resistor, on the clock line of FPGA or DSP, 10Ω, 22Ω, 33Ω are commonly used, and should be placed close to the IC end during PCB layout

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Same answer, damping resistor. The principle is impedance matching.  Details Published on 2022-4-20 13:52
 
 
 

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qwqwqw2088 posted on 2022-4-20 08:50 Damping resistors, on the clock line of FPGA or DSP, 10Ω, 22Ω, and 33Ω are commonly used. They should be placed close to the IC end when PCB layout

Same answer, damping resistor. The principle is impedance matching.

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Thank you. I am very curious about the specific principle. Can you explain how to match impedance? (Because the resistor is connected in series, it is different from the conventional terminal and start matching connection method, and the resistance value is only 33 ohms.) Or can you recommend some reference materials that can help in-depth exploration? Thank you!  Details Published on 2022-4-20 14:49
 
 
 

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qwqwqw2088 posted on 2022-4-20 08:50 Damping resistors, on the clock line of FPGA or DSP, 10Ω, 22Ω, and 33Ω are commonly used. They should be placed close to the IC end when PCB layout

Thanks!

But I'm still a little confused and need to ask:

1. The characteristic impedance of a general high-speed transmission line is 50Ω. Why is there no such common damping resistor value? Are 22 and 33Ω values obtained based on experience or testing?

2. “Place close to the IC” means close to the signal transmitter, right?


Finally, I am still curious about its principle. Baidu searched "damping resistor" but did not find any relevant technical articles, and the answers in the forum only gave a rough concept. Can you point out any reference materials?

Thanks again!

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This aspect is introduced in the signal integrity analysis and can also be found on the Internet   Details Published on 2022-4-20 17:35
 
 
 

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bigbat posted on 2022-4-20 13:52 Same answer, damping resistor. The principle is impedance matching.

Thank you, I am very curious about the specific principle, can you explain how impedance matching is done?

(Because the resistor is connected in series, it is different from the conventional terminal and start-end matching connection method, and the resistance value is only 33 ohms.)

Or could you recommend some reference materials that would help me explore this in depth? Thanks!

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When the internal resistance of the signal source is equal to the resistance of the receiving end, the output power of the signal source is maximum.  Details Published on 2022-4-20 15:02
 
 
 

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RobertLiang posted on 2022-4-20 14:49 Thank you, I am very curious about the specific principle. Can you explain how to match the impedance? (Because the resistor is connected in series, it matches the conventional terminal and starting end...

When the internal resistance of the signal source is equal to the resistance of the receiving end, the output power of the signal source is maximum.

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RobertLiang posted on 2022-4-20 14:46 Thank you! But I am still a little confused and need to ask: 1. The characteristic impedance of a general high-speed transmission line is 50Ω. The common impedance...

This is introduced in the signal integrity analysis

You can also find it on the Internet

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Signal integrity, which introduces the great influence of impedance matching on high-speed signals. You can refer to

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