Understanding the static electricity problems in the field of microelectronics manufacturing from the perspective of integrated circuit back-end manufacturing (chip packaging and testing)

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Understanding the static electricity problems in the field of microelectronics manufacturing from the perspective of integrated circuit back-end manufacturing (chip packaging and testing) [Copy link]

The problems and analysis and solutions of static electricity in microelectronics manufacturing are all in the numerous tiny details.
There are a large number of production processes in microelectronics manufacturing that will generate and accumulate static electricity.
One of the direct effects of static electricity is that the nearby microelectronic devices (to be precise, the large number of metal lines therein) are charged to a high static level through electrostatic induction.

Many electrical test machines involved in microelectronics manufacturing (IC packaging and testing factories contain a large number of electrical testing processes) are typical CDM (Charged Device Model) ESD key processes (100% of CDM ESD will occur). The resulting electrical defects of microelectronic devices (mainly due to excessive leakage current of the insulating film layer in the device, such as gate oxide, ILD, etc.) must be taken seriously and effective control measures must be taken;

The testing sockets in electrical test machines, especially the device loading guide mechanisms therein, are mostly made of insulating plastic or ceramic materials. During the testing process of each device, frictional static electricity will occur between the device package and the test socket guide mechanism. As the test machine tests more and more devices, if the static electricity accumulated on the test socket cannot be effectively eliminated in a timely manner, the risk of electrical failure caused by CDM ESD will increase for the devices tested later.

Currently, ICs based on 28nm process and below account for nearly 50%, and most of them can withstand a maximum CDM ESD voltage of no more than 100V. Among them, the CDM withstand voltage of the latest 7nm and 5nm 5G ICs has dropped to below 50V. Such changes in IC design and process have brought great challenges to the ESD protection in the production process of IC front-end manufacturing - Wafer Fab, IC back-end manufacturing - packaging and testing, and SMT factories.