C6678 multi-core application cache test

Jacktang

C6678 multi-core application cache test [Copy link]

The data coherence problem of L1D cache used by default when C6678 multi-cores exchange data in MSMC
is very troublesome.
A small test verifies that the linesize of L1D cache is
initialized to 64Byte:
if(DNUM == 0)
{
(unsigned int)(0x0C330600) = 0x00;
(unsigned int)(0x0C330604) = 0x100;
(unsigned int)(0x0C330644) = 0x100;
WritebackCache((void *)((unsigned int)(0x0C330600)), 128);
}
Then in the multi-core synchronization interrupt program:
//test

if(DNUM == 0)
{
InvalidCache((void *)(0x0C330600), 64);
(*(unsigned int*)(0x0C330600))++;
WritebackCache((void *)((unsigned int)(0x0C330600)), 4);
}
else
{

InvalidCache((void *)(0x0C330640), 64);
(*(unsigned int*)(0x0C330644))++;
WritebackCache((void *)((unsigned int)(0x0C330644)), 4);
/*
InvalidCache((void *)(0x0C330600), 64);
(*(unsigned int*)(0x0C330604))++;
WritebackCache((void *)((unsigned int)(0x0C330604)), 4);
*/
}

Under such test conditions, the two data always differ by 0x100, but if they are replaced with the code in the commented part, the data integrity will be destroyed.

You can also use XMC to configure SL2, so there is no need to repeatedly perform InvalidCache and WritebackCache operations.