Principle of Sense Amplifier in SRAM

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Principle of Sense Amplifier in SRAM [Copy link]

Principle of Sense Amplifier in SRAM

In SRAM, before the read operation begins, the two bit lines must be precharged and initialized to the same high level. After precharging, the memory cell selected by the word line charges and discharges the bit line. The memory cell size is small, the driving ability is weak, and the bit line load is relatively large, so the two bit lines output voltages with relatively high absolute values (3~3.5V), and the difference between the high and low levels is very small. If it is directly sent to the output buffer, the logic 0 and 1 will not be recognized. Even if it can be recognized, it will take a long time to charge and discharge, which seriously affects the reading speed and data reliability of the SRAM.

The sense amplifier is to amplify the small differential input voltage into a larger output voltage. Due to the heavy load on the differential bit lines in the memory, the voltage on the bit lines changes very slowly. In order to reduce the delay, the voltage on all bit lines must be equal first. Next, when these bit lines are driven, the sense amplifier can detect a small voltage swing and restore it to the normal logic level. By using the formula t∝(C/I)ΔV, where t is the delay of the logic gate, C is the load capacitance, I is the output current, and ΔV is the output voltage swing, we know that the sense amplifier circuit reduces the delay by avoiding waiting for the voltage on the bit line to reach the full swing.

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To reduce latency, the voltages on all bit lines are first equalized. Next, when the bit lines are driven, the sense amplifiers can detect the small voltage swing and restore it to normal logic levels.