LPC2000 series Proteus simulation + code novice's ARM learning notes

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LPC2000 series Proteus simulation + code novice's ARM learning notes [Copy link]

The following is a record of my first stage of learning ARM. During this period, I basically used Proteus and KEIL to do simple experiments (there is a directory of experiments and download addresses at the end). Through this stage of learning, I have an understanding of the basic structure of ARM.

The main learning materials at this stage are "ARM Virtual Development Technology Based on PROTEUS" and another book on ARM architecture. I feel that all books of this type are similar.

The basics needed before learning ARM

• Experience of seniors in learning ARM!
• Master C language programming.
• Understand simple knowledge of microcomputer computing principles, such as binary, the execution process of computer programs, buses (data, address, control), and software systems (system software and application software).
• I've heard of the differences between RISC and CISC, and high-level languages and low-level languages.
• It is best to have heard of serial transmission vs parallel transmission.
• Princeton (ARM7) and Harvard architectures (ARM9, 10, 11—).

What is ARM ?

To learn ARM, you naturally need to understand what ARM is, so as to clarify your learning goals. There is a lot of information on the Internet, "ARM is a company and a processor system"... I will divide learning ARM into the following categories:

• Doing core research and development for ARM. That means working in ARM to develop IP cores, and probably studying electronics or something like that.
• Buy ARM's IP cores and make specific embedded processors and core boards, such as Samsung and NXP.
• Buy an ARM core board, connect peripheral circuits to make a development board for education or development, or directly develop other interrupt products.
• To buy an ARM development board and make a product, you need to develop system software and application software.

3 and 4 are basically on par.

ARM Basics

Any book introducing ARM architecture should include these contents.

Processor Mode

User mode and privileged mode are further divided into system mode, management mode, fast interrupt mode, interrupt mode, termination mode, and undefined instruction termination mode.

2. Register

R0-R7, R15 and CPSR are shared by all modes.
R8-R12 is shared by all modes except RX-fiq in fast interrupt mode.
R13, R14 and SPSR are shared by user mode and system mode only, and others are similar to SPSR.

R15 (PC) Program Counter
R16 (CPSR) Program Rotation Register
R13 (SP) Stack Pointer
P14 (LR) Link Register

ARM instruction set assembly programming

I skipped it. I read it, but didn't use it when doing the Proteus simulation experiment. I forgot about it in two days.

LPC2000

Two of the three introductory ARM books I bought use the LPC2000 series as an example. In fact, you can download the datasheet of the specific LPC2XXX processor from the Internet. The information above is the most authoritative and detailed.

Pin Selection

PINSEL0 and PINSEL1 set the function of each pin.

Interrupt

There are too many interrupt registers to remember.

GPIO

For input and output, take port P0 as an example, the registers are IO0PIN, IO0SET, IO0DIR, and IO0CLR.

Memory

• The available address of LPC2000 is 4GB, 2GB internal (0~0x7FFFFFFF), 2GB external (0x80000000~0xDFFFFFFF), and the upper 0.5GB is the I/O device address space (0xE0000000~0xFFFFFFFF).
• The minimum internal size is 128KB or 256KB Flash.
• The upper 1GB (0x40000000~0x7FFFFFFF) is SRAM, of which 0x40000000~0x40001FFF is on-chip SRAM.
• In the I/O part, the lower 2MB (0xE0000000~0xE001FFFFF) is the VPB peripheral space, and the upper 2MB (0xFFE00000~0xFFFFFFFF) is the AHB peripheral space.
• FLASH acceleration module.

MAMCR sets whether to allow acceleration, and MAMTIM sets the prefetch processor clock.

clock

cclk and pclk
are divided into oscillator mode and slave mode. The oscillator Fosc is up-converted to cclk by PLL, and cclk is divided by VPB to pclk.
Set cclk
PLLCFG Set PLL multiplier M, PLL divider value P
PLLCON PLL enable and connect
PLLSTAT Read PLL status
PLLFEED Make PLL settings effective
For example, Fosc=12MHz, cclk=60MHz, then M=60/12-1=4, because Fcco=P*cclk*2 (requires 156M~320MHz).
Set pclk
by VPBDIV. 00 is divided by 4, 01 is not divided, and 10 is divided by 2.

Timer

pclk timing, the timer is 32 bits, counting from 0 to 0xFFFFFFFF. Taking T0 as an example,
T0TC, the initial value of the counter is
T0PR, the timer counter frequency division is pclk/(PR+1)
T0MR0~3, the match value, when the count reaches the time, different actions are triggered according to the setting of T0MCR.
T0MCR, the action when the counter reaches the match value (reset, interrupt, stop)
T0EMR, the external match register, the operation of the external pin when the match value is reached (MAT0.0~3)
T0CCR, when the external pin has a specific action, the count value is stored in T0CR0~3, set whether to trigger the interrupt
T0CR0~3, and store the TC value under the control of T0CCR.
T0TCR, reset and enable
T0IR, corresponding to MR and CR interrupts

PWM

Watchdog

Pclk is divided by four and controls the 32-bit counter of the watchdog to decrease by one.
WDTC, the initial value of the watchdog counter.
WDMOD, the watchdog working mode, can start and reset the watchdog.
WDFEED, the watchdog feeding register.
WDTV, the current value of the watchdog counter.

UART

Pins RxD0, TxD0
U0RBR, temporarily store received data.
U0THR, temporarily store sent data. When accessing it, the DLAB bit of U0LCR is 0.
U0IER, interrupt enable of serial port status.
U0IIR, interrupt flag.
U0FCR, control UART FIFO (not understood yet).
U0LCR, transmission mode.
U0LSR, current status (error indication).
U0DLL, U0DLM, pclk/(U0DLL U0DLM), the DLAB bit of UOLCR is 1 when accessing.

SPI

Full-duplex synchronous serial interface
Pins:
SCK0, serial clock.
SSEL0, slave select.
MISO, master input, slave output.
MOSI, master output, slave input.
Registers:
S0SPCR, SPI control.
S0SPSR, SPI status.
S0SPDR, SPI data.
S0SPCCR, controls the frequency of SCK. Must be an even number and greater than or equal to 8. (Indicates the pclk cycle in one SCK cycle)
S0SPINT, SPI interrupt.

I2C

Pins: SDA, SCL
Registers:
I2CONSET
I2CONCLR The three registers above
I2CON
control the acknowledge flag, interrupt flag, stop and start, and I2C enable.
I2STAT, I2C status.
I2DAT, I2C data.
I2ADR, I2C slave mode address.
I2STAT, I2C status.
I2SCLH, high level duty cycle in pclk cycles.
I2SCLL, low level duty cycle in pclk cycles.
Frequency division fpclk/(I2SCLH+I2SCLL).

AD conversion

Pins: AIN0~3
Registers:
ADCR, operating mode selection.
ADDR, temporary storage of conversion data and flags.