[align=center][color=#000][size=15px][size=6][b]8[/b][b]bit[/b][b]7[/b][b]segment digital tube driving experiment[/b][/size][/size][/color][/align][align=center][color=#000][size=15px][flash=500,375]h
I'm working on the Viterbi decoder recently. I don't know if anyone has the manual for the viterbi core. When I call it, I get a lot of errors like Error (204009): Can't generate netlist output files
Reprinted from: deyisupport [img]http://www.deyisupport.com/resized-image.ashx/__size/550x0/__key/communityserver-blogs-components-weblogfiles/00-00-00-00-65/7026.aaa.jpg[/img] Today, we see more and
Excuse me, when the IO is configured as the upper edge trigger mode on the msp430, why is the lower edge also triggered, that is, both the upper and lower edges are triggered? Please help me answer th