Location:Training / Embedded Development / FPGA / Verilog HDL digital integrated circuit design principles and applications / User-defined primitive model UDP Delay modeling of basic gate-level primitives and modules

This book systematically introduces Verilog HDL syntax and program design, clarifies the differences between digital synthesizable logic design and test simulation program design in Verilog HDL language, and analyzes typical combinational logic circuits, sequential logic circuits and test programs. The design example provides a relatively complete explanation of the use of Verilog HDL language in digital integrated circuits.

The book has 8 chapters in total. The main content includes an overview of hardware description language and Verilog HDL, the basic syntax of Verilog HDL, Verilog HDL programming statements and description methods, Verilog HDL design and examples of combinational logic and sequential logic, and Verilog HDL integrated circuit test program and testing methods, design examples of more complex digital circuits and systems, EDA tools and use of Verilog HDL in digital integrated circuits, and analysis of the development of Verilog HDL, etc.

Chapter 1 Overview of Verilog HDL digital integrated circuit design method 1
1.1 Development of digital integrated circuits and evolution of design methods 1
1.2 Hardware description language 3
1.3 Development of Verilog HDL and international standards 3
1.4 Verilog HDL and VHDL 5
1.5 Verilog HDL in digital integration Advantages in circuit design 7
1.6 Reusability of functional modules 9
1.7 IP core and intellectual property protection 9
1.8 The role of Verilog HDL in the digital integrated circuit design process 10
Summary of this chapter 11
Questions and exercises 11
Chapter 2 Basic knowledge of Verilog HDL 13
2.1 Language elements of Verilog HDL 13
2.1.1 White space character 13
2.1.2 Comment character 13
2.1.3 Identifiers and escaped identifiers 14
2.1.4 Keywords 14
2.1.5 Values ​​15
2.2 Data types 17
2.2.1 Physics Data types 18
2.2.2 Declaration of wired and register data types 21
2.2.3 Memory type 22
2.2.4 Abstract data types 22
2.3 Operators 24
2.3.1 Arithmetic operators 24
2.3.2 Relational operators 25
2.3. 3 Equality relational operators 26
2.3.4 Logical operators 27
2.3.5 Bitwise operators 27
2.3.6 Reduction operators 28
2.3.7 Shift operators 29
2.3.8 Conditional operators 30
2.3.9 Concatenation and copying Operators 30
2.4 Modules 31
2.4.1 Basic concepts of modules 31
2.4.2 Ports 33
Summary of this chapter 33
Questions and exercises 34
Chapter 3 Verilog HDL programming statements and description methods 35
3.1 Data flow modeling 35
3.2 Behavioral level modeling 37
3.2.1 Procedure statement 38
3.2.2 Statement block 41
3.2.3 Procedure assignment statement 44
3.2.4 Continuous assignment statement 47
3.2.5 Conditional branch statement 49
3.2.6 Loop statement 53
3.3 Structured modeling 57
3.3.1 Module Level modeling 57
3.3.2 Gate-level modeling 64
3.3.3 Switch-level modeling 66
Summary of this chapter 68
Questions and exercises 68
Chapter 4 Verilog HDL digital logic circuit design method 71
4.1 Design ideas and synthesizable features of Verilog HDL language 71
4.2 Design of combinational circuit 74
4.2.1 Digital adder 77
4.2.2 Data comparator 80
4.2.3 Data selector 81
4.2.4 Digital encoder 82
4.2.5 Digital decoder 87
4.2.6 Parity checker 89
4.3 Design of sequential circuit 91
4.3.1 Flip-flop 96
4.3.2 Counter 99
4.3.3 Shift register 100
4.3.4 Sequence signal generator 101
4.4 Finite synchronous state machine 105
Summary of this chapter 115
Questions and exercises 115
Chapter 5 Simulation verification and Testbench writing 119
5.1 Overview of Verilog HDL circuit simulation and verification 119
5.2 Basics of Verilog HDL test program design 120
5.2.1 Testbench and its structure 120
5.2.2 Test platform examples 123
5.2.3 Verilog HDL simulation result confirmation 126
5.2.4 Verilog HDL simulation efficiency 128
5.3 Simulation-related system tasks 129
5.3.1 $display and $write 129
5.3.2 $monitor and $strobe 131
5.3.3 $time and $realtime 133
5.3.4 $finish and $stop 134
5.3 .5 $readmemh and $readmemb 136
5.3.6 $random 137
5.3.7 Value change dump file system task 138
5.4 Signal time assignment statement 142
5.4.1 Syntax description of time delay 142
5.4.2 Description form of time delay 143
5.4 .3 Edge-triggered event control 147
5.4.4 Level-sensitive event control 151
5.5 Tasks and functions 152
5.5.1 Tasks 152
5.5.2 Functions 156
5.5.3 The difference between tasks and functions 159
5.6 Design of typical test vectors 160
5.6.1 Variable initialization 160
5.6.2 Generation of data signal test vector 161
5.6.3 Generation of clock signal test vectors 162
5.6.4 Generation of bus signal test vectors 164
5.7 User-defined component model 166
5.7.1 Definition and calling of UDP 166
5.7.2 UDP application examples 167
5.8 Basic gate-level components and modules Delay modeling 170
5.8.1 Gate-level delay modeling 170
5.8.2 Module delay modeling 174
5.8.3 System tasks related to timing checks 177
5.9 Compiling prepared statements 178
5.9.1 Macro definition 178
5.9.2 File contains Processing 180
5.9.3 Simulation time scale 181
5.9.4 Conditional compilation 182
5.9.5 Other statements 183
5.10 Introduction to Verilog HDL test method 183 Summary
of this chapter 184
Questions and exercises 184
Chapter 6 Verilog HDL advanced programming examples 188
6.1 Digital circuit Hierarchical description method of system design 188
6.2 Typical circuit design 192
6.2.1 Adder tree multiplier 192
6.2.2 Wallace tree multiplier 196
6.2.3 Complex multiplier 198
6.2.4 Design of FIR filter 199
6.2.5 Chip Internal memory design 203
6.2.6 FIFO design 208
6.2.7 Keyboard scan and encoder 212
6.2.8 Verilog HDL design of log function 219
6.2.9 Verilog HDL implementation of CORDIC algorithm 223
6.3 Bus controller design 231
6.3.1 UART Interface controller 231
6.3.2 SPI interface controller 236
Summary of this chapter 240
Questions and exercises 240
Chapter 7 Simulation test tools and comprehensive tools 242
7.1 Introduction to digital integrated circuit design process 242
7.1.1 Design specifications 242
7.1.2 Design division 243
7.1.3 Design input 243
7.1.4 Simulation 243
7.1.5 Synthesis 244
7.1.6 Adaptation routing 244 7.1.7
Timing analysis 244
7.1.8 Physical verification 245
7.1.9 Design end 245
7.2 Test and simulation tools 245
7.2.1 Use of ModelSim 246
7.2.2 Use of NC-Verilog 254
7.3 Synthesis tool 257
7.3.1 Use of Synplify 257 7.3.2
Use of Design Compiler 262
7.4 Testing and synthesis examples 265
7.4.1 Automatic placement and routing 265
7.4.2 Post-simulation 266
7.4.3 Adding the simulation library to ModelSim 268
Summary of this chapter 270
Questions and exercises 270
Chapter 8 Development trends of design and verification languages ​​272
Summary of this chapter 276
Questions and exercises 276
References 277