Zhou Ligong verilog

This tutorial mainly introduces the basic syntax of Verilog HDL, such as: Common Verilogy syntax: module structure, data types, operators and expressions, assignment statements and block statements, conditional statements, loop statements, generation statements, structure descriptions, tasks and functions Description statements, commonly used system tasks, system tasks for debugging, commonly used compilation preprocessing statements, etc., were recorded by Guangzhou Zhouligong Microcontroller Technology Co., Ltd.

• Chapter 1：1-2 (21 minutes and 7 seconds)

• Chapter 2：3-4 (24 minutes and 53 seconds)

• Chapter 3：5 (9 minutes and 46 seconds)

• Chapter 4：6 (23 minutes and 9 seconds)

• Chapter 5：7 (12 minutes and 56 seconds)