Design of 20-bit Σ-Δ stereo ADA circuit TLC320AD75C

    Abstract: The characteristics and composition of Σ-Δ ADC and DAC are introduced, and the analog and digital audio data interface technology of Σ-Δ stereo ADA circuit TLC320AD75C, the serial control interface technology of DAC and the use of such devices are discussed in detail Precautions.

    Keywords: Σ-ΔADC/DAC TLC320AD75C audio data interface

    1 Σ-Δ ADC and DAC

    Most of the A/D converters used today, such as parallel comparison type, successive comparison type, integral type, etc., are linear pulse code modulation (LPCM) type A/D converters [1]. An A/D converter of this type with a resolution of n bits requires a rather complex comparison network and extremely high-precision analog electronics in order to be able to distinguish 2n different quantization levels. When the number of bits n is high, the implementation of the comparison network is very difficult, thus limiting the improvement of the converter resolution. When an A/D converter is used to form an acquisition system, the sampled values ​​must be sampled and held before conversion. The higher the resolution of the A/D converter, the more important this requirement is. Therefore, in some high-precision acquisition systems, In addition to the anti-aliasing filter at the front end of the A/D converter, most of them also need to set up a special sampling/holding circuit, thus increasing the complexity of the acquisition system.

    The so-called summed incremental modulation coding (Σ-Δ) type A/D converter is different [2]. The LPCM type A/D converter completely ignores the correlation between signal samples and only directly performs quantization coding based on the size of each sample of the sampling data; while the Σ-Δ type A/D converter performs quantization coding based on the previous The difference between the value and the next value is the so-called increment size for quantization encoding. A Σ-Δ A/D converter generally consists of two parts. The first part is an analog Σ-Δ modulator, and the second part is a digital decimation filter, as shown in Figure 1(a). The Σ-Δ modulator samples the input analog signal at a very high sampling frequency (much higher than the Nyquist sampling frequency) and performs low-bit quantization (usually 1 bit) on the difference between the two sampled values. Thus, a Σ-Δ code represented by a low-digit number is obtained, and then this Σ-Δ code is sent to the second part of the digital decimation filter for decimation filtering, thereby obtaining a high-resolution LPCM signal. Figure 1(b) shows the corresponding Σ-Δ type D/A converter. This type of A/D and D/A converters, in terms of quantization, avoids the need to manufacture high-bit D/A converters or high-precision quantizers in LPCM-type A/D converters due to the use of extremely low-bit quantizers. The difficulty of the resistor network; and because it uses Σ-Δ modulator technology and digital decimation filters, it can obtain extremely high resolution, which greatly exceeds the LPCM type A/D converter; furthermore, due to the low code bits, sampling and quantization Encoding can be completed at the same time and takes almost no time, so there is no need for a sample and hold circuit, which greatly simplifies the composition of the acquisition system. Compared with the traditional LPCM A/D converter, the Σ-Δ A/D converter actually uses a high sampling rate in exchange for high bit quantization, that is, a solution that exchanges speed for accuracy. Since the 1990s, Σ-Δ A/D and D/A converters have achieved great development and are used in high-precision data acquisition, especially in the fields of digital audio systems, multimedia, seismic exploration instruments, sonar, electronic measurements, etc. has been widely used.

    2 Introduction to TLC320AD75C

    The TLC320AD75C is a high-performance 20-bit stereo analog-to-digital and digital-to-analog converter (ADA) using fourth-order Σ-Δ technology. It can simultaneously perform four-channel 20-bit resolution analog-to-digital (A/D) and digital-to-analog (D /A) Conversion of signal channels. Other features include digital attenuation, digital recovery filtering, soft mute and on-chip timing and control [3]. The chip has the following features:

    ·Single 5V (analog/digital) power supply level and 3.3V to 5V digital interface levels

    ·Sampling rate up to 48kHz;

  ·The resolution is 20 bits;

    ·The signal-to-noise ratio of the ADC is 100dB;

    ·The total harmonic distortion + noise of ADC is 0.0017%

    ·The signal-to-noise ratio of the DAC is 104dB;

    ·The total harmonic distortion + noise of DAC is 0.0013%;

    ·Internal power reference;

    ·Serial interface;

    ·Differential structure;

    ·DAC has PWM output;

    ·Digital restoration filtering can be performed at DAC sampling rates of 32, 44.1 and 48kHz;

    ·DAC has digital attenuation/soft mute function.

    For the pin arrangement and pin functions of TLC320AD75C, please refer to TI's product data manual. Its functional block diagram is shown in Figure 2 .

    3 Interface circuit design of TLC320AD75C

    It can be seen from the functional block diagram of TLC320AD75C that the interface between TLC320AD75 and external circuits mainly consists of three parts: one is the interface between TLC320AD75C and analog audio data, including the differential input of ADC and the PWM output of DAC; the other is the interface between TLC320AD75C and the microcontroller. Digital audio data interface; the third is the serial control interface of the DAC. The specific circuit design is given below.

    3.1 Interfacing with analog audio data

    In order to provide a high common-mode noise rejection ratio and increase the input dynamic range, the input of the TLC320AD75C ADC adopts a differential form; at the same time, it is also necessary to consider that the TLC320AD75C has high speed and resolution, switched capacitor input structure and single power supply operation. This requires that we must carefully design the relevant drive amplifier. The driver amplifier must provide a low source impedance and sufficient output current to drive the ADC input, and its high-frequency output impedance must be low enough to avoid conversion errors. Figure 3 shows the interface circuit between TLC320AD75C and analog audio data. Since the left and right channel circuits are exactly the same, only one channel's interface circuit is drawn. U1, U2 and U3 all use ultra-low noise, wide-band, high-precision, high-speed operational amplifier OP37. U1 and U2 convert the unipolar audio input into a differential output, and U3 converts the differential signal pair L2-L1 (PWM signal) output by the TLC320AD75C into a unipolar signal. The +5V in U1 provides a +2.5 static bias to the non-inverting terminal of the op amp through two 100KΩ resistors, and a 100μF capacitor connects it to AC ground. The non-phase termination method of U2 is the same as that of U1, which is not shown in Figure 3.

    3.2 Interface with digital audio data

    The serial port of TLC320AD75C has two working modes: when the M/S pin is high level, the ADC serial port is configured as the master mode, and TLC320AD75C generates LRCKA and SCLKA from MCLKI; when the M/S pin is connected to low level, it is the slave mode. , the device receives LRCKA and SCLKA externally.

    This article takes the ADC master mode as an example to illustrate the interface between TLC320AD75C and the microcontroller. In master mode, LRCKA is generated internally by MCLKI, and LRCKA is fixed to the sampling frequency fs (MCIKI/256). During the high period of this signal, the left channel data is serially shifted to the output; during the low period, the right channel data is shifted to the output. The conversion period is synchronized by the rising edge of LRCKA. The three waveforms (a), (b), and (c) in Figure 4 represent the 20 bits and MSB shifted out from the TLC320AD75C in the first 20 cycles of the 32 SCLKA cycles used for the left and right channel data. ADOUT data before.

    As can be seen from Figure 4, the interface between TLC320AD75C and microcontrollers with synchronous serial ports such as TI's DSP series TMS320C2X/3X/5X/2XX/54X is quite easy. However, the development and application of DSP in our country is not yet widespread at present, and a large number of scientific and technological and engineering technicians are relatively unfamiliar with DSP. In contrast, microcontrollers such as MCS51, 8098, and MCS196 series are quite popular and widely used in our country. Unfortunately, the MCS51 series of microcontrollers does not have a synchronous serial port, and the output of a large number of current data acquisition systems requires parallel data. Considering the above situation, in order to interface with the MCS51 series, it is necessary to design a series-to-parallel circuit and a parallel-to-series circuit on the premise of meeting the timing sequence in Figure 4.

   Figure 5 is the ADC and MCS51 interface circuit of TLC320AD75C. The DAC interface circuit is the reverse process of the above circuit. Just change the 8-bit output latch shift register (three-state, serial input and parallel output) 74LS595 into an 8-bit input latch shift Register 74LS597 (three-state, parallel input and serial output) is enough, and will not be described in detail here. Figure 5 is drawn in the same way as Figure 3. Due to space limitations, some circuit details are omitted. Readers should add them when applying the circuit in this article. The following briefly describes the working process of the circuit shown in Figure 5. According to the serial interface timing sequence in Figure 4, it is required to use LRCKA and SCLKA to generate the pulse shown in Figure 4(d). During the high level of the pulse, 20-bit serial data is sent to the serial input and parallel output interface circuit composed of three cascaded 74LS595s; on the falling edge of the pulse, the data in the shift register in the 74LS595 is transferred to the latch device; during the low level of the pulse, an interrupt is sent to INTO of MCS51. MCS51 sends out three chip select signals in sequence and reads out the 20-bit data, thus completing the collection of one channel. Therefore, how to generate the pulse shown in Figure 4(d) is the core issue of this circuit. In the circuit shown in Figure 5, the rising and falling edges of LRCKA captured by the 74LS123 are generated through a wired AND method to generate an extremely narrow pulse in the form of Figure 4(e). Set 74LS74 during the low level of the pulse; two pieces of 74LS160 are connected into a decimal counter, counting SCLKA when the 74LS74 outputs a high level, and outputs a high level pulse when 20 pulses are counted. This pulse is inverted through a NOT gate and goes to the reset terminal of the 74LS74. 74LS74 generates the pulse shown in Figure 4(f) under the above-mentioned setting and reset. At the same time, it also clears the counter during the low level of the pulse and stops the counter until the next high level of the pulse. arrival. It should be pointed out that the pulse shown in Figure 4(f) has a delay compared with the pulse shown in Figure 4(d), but as long as the delay time is less than TSCLKA/2, that is, the rising edge ratio of the pulse shown in Figure 4(f) starts to change. After the first rising edge of SCLKA is early, the synchronous counter can count correctly without missing 1 bit of serial data.

    3.3 DAC serial control interface

    The 16-bit control data input performs the control functions of the device. The TLC320AD75C uses the most significant bit first format, so for a 16-bit data word, D16 is the most significant bit (MSB) and D1 is the least significant bit. Figure 6 shows the input timing of CDIN, SHIFT and LATCH. While LATCH is low, data is loaded internally. CDIN is a 24-bit data stream, including 16-bit control data D1~D16 and 8-bit device addresses A1~A8. Figure 7 shows the interface circuit of TLC320AD75C and MCS51 serial port. In mode 0 state, the serial port of MCS51 is in synchronous shift register mode, data enters and exits from the RXD terminal, and the synchronous shift pulse is output from the TXD terminal. Since the MCS51 sends and receives 8-bit data with the low bit first, while the TLC320AD75C uses the most significant bit first format, the high and low bits of the data should be reversed in the MCS51 software.