Design and implementation of digital filter based on FPGA

In the process of information signal processing, such as signal filtering, detection, prediction, etc., filters are used. Digital filters are the most widely used method in digital signal processing. Commonly used digital filters have infinite length units. There are two types of impulse response (IIR) filters and finite length unit impulse response (FIR) filters [1]. For application designers, due to the high requirements for development speed and efficiency, it is impossible to fully understand the optimization technology related to digital filters in the short term, and it takes a lot of effort to make the designed filters superior in speed, resource utilization, and performance. tend to be better. To use a debugged IP core, you need to purchase it from Altera. This article adopts an FPGA design method based on DSP Builder, taking the implementation of a low-pass 16th-order FIR filter as an example. Through the generated filter top module file and A/D module file design, in the NC of Lianxing Technology -EDA-2000C experimental box verified that the digital filter circuit designed using this method works correctly and reliably and can meet the design requirements.

1 Parameter design of FIR filter

1.1 Design requirements

The digital filter is actually a linear non-time-varying discrete system implemented using a limited precision algorithm. Its design steps are to first determine its performance indicators according to needs, design a technical indicator required for system function H(z) approximation, and finally use Limited precision algorithm implementation. The design indicators of this system are: design a 16th-order low-pass FIR filter, the sampling frequency Fs of the analog signal is 48KHz, the required cut-off frequency of the signal Fc=10.8kHz, and the input sequence is 9 bits wide (the widest bit is sign bit).

1.2 Parameter selection of FIR filter When designing a frequency-selective digital filter, it is usually hoped to have an approximately constant frequency response amplitude and to minimize the phase distortion in the passband. A linear phase with an integer slope corresponds to a simple linear phase in the time domain. The delay can reduce the phase distortion to the minimum in the frequency domain [2]. Use FDAtool, a special toolbox for filter design provided by Matlab, to simulate and design the filter to meet the required amplitude-frequency characteristics of the FIR filter. ,As shown in Figure 1.

2 DSP Builder design of digital filter

2.1 Introduction to DSP Builder

DSP Builder is a digital signal processing (DSP) development tool launched by Altera. It integrates Mathworks' Matlab and Simulink DSP development software in the Quartus II FPGA design environment [3]. For DSP Builder, it includes DSP system modeling, system-level simulation, conversion of design model to VHDL hardware description language code, RTL (Register Transfer Level, logic synthesis) level functional simulation testing, compilation adaptation, placement and routing, and timing. From real-time simulation to programming and configuration of DSP target devices, the entire development process can almost be completed in the same environment as the top-level development tool Matlab/Simulink.

2.2 Establishment of FIR filter algorithm model

According to the principle of FIR filter, FPGA can be used to implement the FIR filter circuit. The first step of the DSP Builder design process is to enter the design in Matlab/Simulink, that is, create an MDL model file in the Simulink environment of Matlab and call Altera graphically The graphics modules in DSP Builder and other Simulink libraries form a system-level or algorithm-level design block diagram (or Simulink modeling).

2.3 System-level simulation based on DSP Builder

The input signal is superimposed using two sinusoidal signals with frequencies f1=8KHz and f2=16KHz respectively. The simulation waveform is shown in Figure 2. From the simulation results of the FIR filter circuit, it can be seen that the output signal after the input signal passes through the filter is basically It becomes a sinusoidal signal with a single frequency, and the model simulation is completed.

3 Implementation of digital filter based on FPGA

3.1 Use Modelsim for functional simulation

The simulation performed in DSP Builder is of a system verification nature. It simulates the MDL file and does not simulate the generated VHDL code. In fact, the generated VHDL description is at the RTL level and is targeted at specific hardware structures. There may be differences in software understanding between the two. The converted VHDL code implementation may not be completely consistent with the situation described by the MDL model. This requires functional simulation of the generated RTL-level VHDL code.

We use Modelsim to perform functional simulation on the generated VHDL code. Set the input and output signals to be in analog form, and the simulation waveform shown in Figure 3 will appear. You can see that this is basically consistent with the simulation results in Simulink. It can be used for hardware design in the Quartus II environment [4].

3.2 Implement FIR filter in FPGA device

The digital filter implemented in FPGA processes digital signals. In practical applications, the analog signal must first be sampled and quantized using an A/D converter. Most of the traditional methods are completed by CPU or microcontroller. The disadvantages are long control cycle and slow speed. Using a synchronous sequential state machine to control A/D sampling is an effective method that is both simple and reliable and can significantly increase the sampling period.

Design the state machine as required in the Quartus II environment through VHDL language and convert it into a .bsf file; open the Quartus II project files fir.qpf and fir.vhd created by DSP Builder and convert them into the corresponding .bsf file, so that the corresponding The designed module is shown in Figure 4. These two modules are called to create a new top-level schematic file. Through timing simulation in the software environment, the device pins are specified, compiled, and finally downloaded to the EP1K10TC100-3 device in the experimental box. .

4 Conclusion

Use the signal generator to generate the required two sinusoidal signals of different frequencies, and you can see the filtered results on the oscilloscope. When you need to design different filter circuits, you can only modify the filter model file. It can be seen that when using FPGA to develop digital filters, using DSP Builder as a design tool can quickly and reliably design practical filter systems.