My summary of learning FPGA

People who read this article: familiar with the basic knowledge of digital circuits (such as adders, counters, RAM, etc.), familiar with basic synchronous circuit design methods, familiar with HDL language, have some understanding of the structure of FPGA, and have a relatively good understanding of the FPGA design process.

I. Preface

1. Benefits of FPGA

Design engineers no longer need to draw cumbersome schematics and PCB connections, thus shifting the focus of work to functional implementation, greatly improving work efficiency; with the promotion of HDL (Hardware Description Language) hardware description language synthesis tools and other related tools, the application of FPGA has increased.

2. Some bad habits of engineers when using FPGA

Any matter is divided into two parts, and there are pros and cons.

We find that more and more engineers now do not care about the implementation form of their own circuits, thinking "I just need to describe the function correctly, and leave the rest to the tools."

Under the influence of this idea, when engineers use HDL language to describe circuits, they have no circuit concept in their heads, or it is very vague; they also don’t know what the code they write will look like after synthesis, what it will look like when mapped to the chip, and whether some special resources of FPGA are fully utilized. When encountering problems, the first thing that comes to mind is to replace FPGA devices with faster speed and larger capacity, which leads to an increase in material costs; what is more fatal is that due to the lack of understanding of device structure, and even less understanding of the design skills closely related to device structure, over-reliance on synthesis tools, the tools are not good, and you are helpless, resulting in the problem being delayed in solving, which seriously affects the development cycle and causes a sharp increase in development costs.

3. Knowledge that should be possessed to learn FPGA

well At present, our design scale is getting larger and larger, and circuits with millions of gates and millions of gates are common. At the same time, the device technology we use is becoming more and more advanced, and we have entered the deep submicron era. When dealing with deep submicron devices, our design methods will inevitably change, and we must pay more attention to the line delay that was rarely paid attention to before (I believe that ASIC design will be the same in the future).

If we do not improve our design methods and design skills, we will not be able to face these huge circuit designs based on deep submicron technology. Moreover, the current competition is becoming more and more intense. From the perspective of saving company costs, we are also required to complete more functions in relatively small devices as much as possible. 2. Talk about several key issues of FPGA tools 4. About our understanding of the problem of over-reliance on FPGA tools The emergence of hardware description language and synthesis tools has greatly improved the work efficiency of engineers. However, with their popularization and promotion, a bad phenomenon is gradually spreading; in the design process, only focus on whether the function is realized, without considering or rarely considering how the circuit is realized; over-reliance on synthesis and other tools to improve design performance (such as speed, area, etc.), rather than considering whether the circuit itself is optimal. If the design is regarded as a chemical change, then the tool only plays the role of a catalyst, and the background knowledge, circuit design methods and related skills we have mastered are the molecules participating in the chemical reaction and the decisive factors. Therefore, when the design encounters difficulties, we cannot rely entirely on the tools, let alone blame the tools. Only we are the key to determining the success or failure of the design. 5. No matter what kind of synthesis tool is used, it includes two processes Process 1: It is to convert the behavior-level description into the gate-level description through a certain algorithm. This process has nothing to do with the design process library and the user constraints. Process 2: It is to map the converted gate-level description to the device in the corresponding process library through an algorithm under the user's constraints. For ASIC, it is mapped to the manufacturer's Gate library, and for FPGA, it is mapped to the unit structure of the FPGA device. From the above two steps, we can see that when the style of the design code is different, the performance of the design is largely determined in the first step of synthesis (for ASIC, because it is converted into Gate, the device library is generally Gate, so the impact is relatively small). Therefore, it is not difficult for us to understand the importance of code style to FPGA design. 6. Talk about the specific performance of synthesis tools The inconsistent targets of different synthesis tools and the different performance of each synthesis tool lead to different synthesis results. At present, the main synthesis tools include DC (Design Compiler), FC2 (FPGA Compiler II), Synplify, Leonardo, Galileo and other synthesis tools: 1) DC: mainly used for ASIC synthesis tools 2) FC2: is an enhanced version of DC in FPGA synthesis 3) Leonardo: is a pioneer in FPGA synthesis tools 4) Synplify: is the fastest growing synthesis tool (produced by Synplicity) No matter which synthesis tool, the synthesis of FPGA must be closely combined with the FPGA structure of each FPGA manufacturer, otherwise it will not be possible to better utilize the advantages provided by FPGA; from the current point of view, Synplify or Leonardo synthesis tools are preferred; DA's FPGA synthesis performance is poor but it is suitable for ASIC synthesis. So far, third-party synthesis tools have not been able to make good use of FPGA devices because the code style has not kept up, resulting in poor performance. 7. Importance of logic code style Because the synthesis tool cannot make the most of the superior performance provided by the device, the final product performance deteriorates; if you want to get better performance, it is required that in FPGA design, it is best to use some cores for some designs (but this code design based on FPGA devices (unique process) will reduce the reuse performance of the design code and the compatibility of FPGA design and ASIC design). 8. Example: Taking Xilinx as an example, how can we adopt an appropriate code style to improve circuit performance: 1) The application of resource sharing is limited to the same module. In this way, the synthesis tool can maximize its resource sharing synthesis function. 2) All related logic on the critical path is placed in the same module as much as possible. In this way, the synthesis tool can exert its best synthesis effect. 3) The module where the critical path is located is synthesized separately from other modules, and the speed-first synthesis strategy is adopted for the critical path, and the area-first synthesis strategy is adopted for other modules. 4) Register all outputs as much as possible. Doing this makes it easier to add constraints; at the same time, the combinational logic on a path cannot be scattered in various modules, which is very beneficial to synthesis. It is relatively easy to achieve the goal of win-win in terms of area, area and speed. 5) The size of a module cannot be too large. The specific size is determined by each synthesis tool. 6) A module should have only one clock, or the entire design should have only one clock.