High-speed real-time control system composed of DSP and 80C196 dual CPU

DSP is also called digital signal processor. TMS320C31 is the third DSP chip of TI. Its basic structure includes: (1) bus structure that separates program memory from data space, which can address and access the two independent memories, program memory and data memory, independently; (2) pipeline structure. Taking the three-stage pipeline operation as an example, in each instruction cycle, three different instructions are active, but in different stages, namely instruction fetch, decoding and execution; (3) dedicated hardware multiplier, so that multiplication can be completed in a single cycle; (4) special DSP instructions; (5) fast instruction cycle, which can reach 33.3ns, that is, 60M instructions can be executed per second.

A complete control system can be formed by a TMS320C31 plus memory, analog/digital conversion unit and peripheral interface, but this solution is not feasible to achieve high-speed real-time control. Because TMS320C31 not only needs to complete complex algorithms, but also needs to collect and process data, control the actuators in the external system and realize the human-machine interface, and these tasks will inevitably greatly extend the system's control cycle of the control object. Therefore, we use TMS320C31 and a general-purpose microprocessor 80C196 as the CPU of this high-speed real-time control system. Among them, 80C196 is the host, responsible for data collection and processing, control and drive of the actuators in the external system, and human-machine interface functions; TMS320C31 is the slave, responsible for the implementation of complex algorithms. In this way, TMS320C31 can focus on the calculation of the algorithm and make full use of its high-speed data processing capabilities. TMS320C31 and 80C196 use dual-port RAM for high-speed data communication. The reason for using dual-port RAM is that this communication method has a high data transmission rate and good anti-interference performance.

1 System Configuration

The system is mainly composed of two modules: algorithm module and input-output control module. The algorithm module is composed of TMS320C31 as the core, which is the computing center of the whole system and is responsible for the realization of complex algorithms; the input-output control module is composed of 80196 as the core, which is responsible for data collection and processing, control and drive of actuators in external systems, and human-machine interface. The algorithm module and the input-output control module communicate with each other at high speed through the dual-port RAM IDT7140. The algorithm obtains the input data required by the algorithm (that is, the data sampled in real time) from the input-output control module, and then sends the calculation results to the input-output control module, and finally the input-output control module controls each actuator.

2 Interface circuit between TMS320C31, 80C196 and dual-port RAM IDT7140

As shown in Figure 1, IDT7140 has two sets of completely symmetrical address lines, data lines and control lines.

TMS320C31 is connected to the left group of wires, and 80C196 is connected to the right group of wires. TMS320C31 allocates the address space of 0x20000H to 0x1003ffH to IDT7140. GAL16V8 decodes A[20,23] and the external access selection signal /STRB to give the chip select signal /CEL of IDT7140. IDT7140 works in interrupt mode by connecting the /BUSYL and /BUSYR pins to a high level. The interrupt signal /INTL of IDT7140 can be directly connected to an external interrupt pin of TMS320C31 (here, external interrupt 1, INT1, is allocated to the dual-port RAM IDT7140). The specific reason will be explained in Part 3. 80C196 allocates the address space of 0xA000H to 0xA3ffH to IDT7140. GAL16V8 decodes AD[12,15] and external memory read signal /RD to give the chip select signal /CER of IDT7140. 80C196's /WE is low level in the write cycle and high level in the read cycle, which is consistent with the definition of R/WR of IDT7140, so /WE can be directly connected to R/WR as the read control signal on the right side of IDT7140. The interrupt pin /INTR of IDT7140 is connected to the external interrupt of 80C196.

3 Interrupt Logic Design of Dual-Port RAM IDT7130/40

Dual-port RAM must use a certain mechanism to coordinate the read and write operations of the left and right CPUs. IDT's dual-port RAM series uses four methods: port interrupt, hardware, token and software to coordinate the two sides. In the high-speed real-time control system composed of TMS320C31 and 80C196 dual CPUs, IDT7140 uses the interrupt method. The following introduces the interrupt logic design of IDT dual-port RAM series.

As shown in Figure 2, the interrupt logic of the IDT dual-port RAM is actually composed of two basic RS flip-flops composed of NAND gates. In all IDT dual-port RAM chips, the top two units of the memory are used as interrupt mailboxes for the left and right CPUs. Taking the 1K dual-port RAM as an example, these two units are 3FEH and 3FFH. Among them, 3FEH is the interrupt mailbox of the left CPU, and 3FFH is the interrupt mailbox of the right CPU. Each CPU can only read its own interrupt mailbox and write the other party's interrupt mailbox; but cannot write its own interrupt mailbox and read the other party's interrupt mailbox. When the 3FFH unit of the interrupt mailbox of the right CPU in the left CPU writes data, /WR in Figure 2 is set to 0, IRn+1 is set to 1, and the interrupt signal pointing to the right CPU is valid; when the right CPU reads data from its own interrupt mailbox 3FFH unit, /RR in Figure 2 is set to 0, then IRn+1 is set to 0, and the interrupt signal pointing to the right CPU is cleared. Similarly, the setting and clearing of the interrupt signal of the left CPU by the right CPU is the same, except that the upper 3FFH unit is replaced by the 3FFH unit. Its truth table is shown in Table 1.

Table 1 Dual-port RAM interrupt logic truth table

It is not difficult to see from Figure 2 and Table 1 that the interrupt signal pointing to the right CPU is valid from the moment it is set to a low level until the right CPU reads the 3FFH unit. TMS320C31 requires that an external interrupt must remain at a low level for at least one H1 cycle in order to be confirmed by TMS320C31. If the external interrupt signal remains low within one to three H1 cycles, only one interrupt is confirmed; if it remains low for three or more cycles, more than one interrupt can be confirmed. Therefore, the effective time of the interrupt signal provided by IDT7140 can meet the requirements of TMS320C31, so that the /INTL pin of IDT7140 can be directly connected to the INT1 of TMS320C31. But at the same time, TMS320C31 is also required to serve the interrupt request of IDT7140 as soon as possible to avoid one interrupt request being mistaken for multiple interrupt requests.

4 Software Implementation of High-Speed ​​Data Communication between TMS320C31 and 80C196 Using Dual-Port RAM

From Figure 2, we know that when the left CPU writes to the interrupt mailbox 3FFH unit of the right CPU, the dual-port RAM will send an interrupt signal to the right CPU; similarly, when the right CPU writes to the interrupt mailbox 3FFH unit of the left CPU, the dual-port RAM will also send an interrupt signal to the left CPU. Take the TMS320C31 on the left as an example. After it receives the external interrupt signal INT1, it does not know whether the 80C196 on the right has just started to occupy the dual-port RAM or has finished using it and wants to release the right to use it, or other meanings. Therefore, both parties should have a simple agreement in advance. For example, when the right CPU writes "FFH" in the 3FEH unit (or the right CPU writes "11H" in the 3FFH unit), it means that the right (left) side is occupying the dual-port RAM, and it means that it wants to release the right to use it. Or there can be more definitions of data meanings, depending on the complexity of the communication content of the two CPUs. For example, in this high-speed real-time control system, "88H" and "55H" are also defined to represent other meanings. In this way, corresponding operations can be performed in the interrupt service program. The following takes TMS320C31 as an example to illustrate the software implementation of data communication. The program flow is shown in Figures 3 and 4.

As various complex algorithms are applied more and more widely, DSP will be more and more popular, and various multi-CPU systems will emerge. In these systems, dual-port RAM will become the communication channel in many multi-CPU systems with its convenient and fast characteristics.