DSP-based banknote number identification system

　　 1 Introduction

　　In recent years, coins, especially banknotes, have been robbed continuously, which has seriously affected social security and caused serious economic losses to banks. If the robbed coins cannot circulate in the market, it will inhibit the occurrence of bank robberies from one aspect. One solution is to record the numbers on each bundle of banknotes and create a database of stolen banknote numbers. Provide an automatic banknote number identification device in the currency circulation market, for example, combined with a banknote counting machine, to compare the currency number identification data with the robbed number database. Once the same number appears, it can be confirmed that the currency currently in circulation is robbed. coins, thereby limiting their circulation and also facilitating the detection of robbery cases. In addition, due to the uniqueness of banknote numbers, identifying the numbers on banknotes can help identify counterfeit banknotes. There is a banknote verification and numbering machine abroad that can automatically identify and print numbers on typical banknotes, such as US dollars, pounds, etc. The typical recognition speed of this device is 1 sheet/second. However, there are no literature reports on automatic number recognition devices attached to banknote counting machines.

　　In recent years, some domestic units have developed automatic banknote number recognition devices. For example, Nanjing University of Aeronautics and Astronautics has developed a banknote number recognition system based on a single-chip computer [3], which uses a linear array CCD to collect banknote images and a single-chip microcomputer. Location and identification of numbers. The main problem is that it is difficult to improve the number recognition speed. Harbin Institute of Technology developed a DSP -based banknote number recognition system [4], with a recognition speed of 8 sheets/second. However, this speed is a simulation result on a PC and has not been implemented in the actual prototype. In addition, the system uses CIS (contact line image sensor) to obtain the banknote image signal, and there is a problem of sensor wear.

　　In response to the above situation, this article proposes a banknote number identification system based on DSP, which uses an area array CCD camera to collect banknote number images, that is, 25 images are collected per second, while the current banknote counting machine counts money per second. It takes about a dozen sheets per second, so it can be used in conjunction with a money counting machine. The system consists of the following parts: (1) Using Philip's professional video decoder SAA7113 to realize the digitization of banknote number images; (2) Using TI's digital signal processor TMS320VC5410 to realize the collection and processing of digital banknote number images; ( 3) Use TI's asynchronous serial interface chip TL16C550 to complete the communication between the entire system and the PC.

　　2 Hardware design principles

　　The working principle of the DSP-based banknote number recognition system: the banknote analog video image taken from the area array CCD camera is converted into a digital image by a professional video decoder. The digital video signal is stored in the data space of the DSP through the image cache FIFO as a data source for subsequent image recognition. The video decoder simultaneously separates the horizontal and vertical synchronization signals and the pixel clock reference signals as control signals for the image buffer module. In order to save and record the numbers, the identified banknote number data is stored in the fast flash memory FLASH, or transmitted to the PC through the asynchronous serial port as needed. The complex programmable logic device CPLD plays the role of global logic control in the entire system and window processing of the collected banknote images. The overall structural block diagram of the system is shown in Figure 1.

　　3 Image acquisition module

　　3.1 Application of video decoding chip SAA7113 in the system

　　SAA7113 is a highly integrated video decoder that supports interlaced scanning and multiple data output formats. The built-in I2C interface provides simple control functions for the chip's internal circuits. The control of SAA7113 mainly includes preprocessing of input analog signals, control of chroma and brightness, output data format and selection control of output image synchronization signals, etc.

　　The image recognition processing in the entire system is mainly carried out for grayscale images. Among the various data output formats provided by SAA7113, the RAW format directly outputs the image corresponding to the pixel clock on the 8-bit output pin. Compared with other formats, this data format will be more direct in collecting grayscale images.

　　The output RTS0 and RTS1 of SAA7113 are multi-function multiplexing pins. By writing different control words to the sub-address register SA12, the two output pins can be configured as different signals such as horizontal synchronization, frame synchronization, and odd-even field synchronization. In this system, RTS0 is set as the horizontal synchronization signal, and RTS1 is set as the field synchronization signal. At the same time, SAA7113 also outputs the synchronization reference signal LLC of the pixel clock.

　　Set each control register of SAA7113 through the I2C bus protocol to meet the system requirements. Since the DSP chip is a processing device, its control capability is relatively weak and there are few general-purpose I/O ports, while the microcontroller has good control functions. Therefore, the initialization work of SAA7113 is completed using the AT89C51 microcontroller. There is no hardware I2C bus interface inside the AT89C51 microcontroller. Here, the P1.0 port of the microcontroller is set as the serial data line SDA, and P1.1 is set as the serial clock line SCL. The I2C bus is simulated through software to initialize the video decoder SAA7113. , its hardware principle is shown in Figure 2.

　　3.2 Use CPLD to implement windowing processing of images

　　VHDL program that uses pixel clock LLC2 and horizontal synchronization signal HS to implement line interception:

　　process(LLC2,HS)
　　variable temp: std_logic_vector(10 downto 0);
　　begin
　　 if(LLC2'event and LLC2='1') then
　　if(HS ='1' )? then? temp:=temp+'1';
　　if(temp>80 and temp<241)
　　then Href<='1';
　　else Href<='0';
　　end if; else Href<=' 0';
　　end if; end if;
　　end process;

　　The digital video image output from SAA7113 is the entire image, but the image size useful for recognition is 40x200, in order to reduce the storage and processing of image data. By adjusting the position between the CCD camera and the money counter, using the horizontal and field synchronization signals HS, VS and pixel clock reference signal LLC of the video decoder, and using VHDL language, the windowing process is performed on the image area of ​​interest. The specific method is: during the period when the field signal VS is high, the row signal HS is counted, so that the field signal output is high during the image period of interest, and the field signal is low in other areas, thus obtaining a new field signal VREF. Similar to field interception, a new row signal HREF is obtained using the row signal HS and the pixel clock LLC2. In this way, the windowing process of the image is realized through two counters. This article gives a block diagram for windowing an image and a VHLD program for row interception. The VHDL program for column interception is similar to row interception.

　　3.3 Use DSP to realize image collection

　　SAA7113 will always be in working state after power-on initialization. Its pixel clock reference signal LLC is 27MHz, which is twice the pixel clock, that is, the pixel clock is 13.5MHz. If the image acquisition is performed directly with such a fast clock frequency, data loss will occur. This article uses a first-in-first-out array FIFO as the image cache. The image data is first stored in the FIFO, and the image data in the FIFO is read through the DSP to complete the image collection. The CCD camera outputs a PAL video signal with a field frequency of 50Hz, a line period of 64us, and a field period of 20ms. In this system, the image size is 40x200. It can be seen through the oscilloscope that the field period after interception is 2.56ms, and the read and write cycle of DSP is 10ns. The time required for the read and write program through DSP is about 3ms, which is the same as that of the currency counter. Connected, there will be sufficient time to achieve image collection.

　　Since FIFO does not have chip select, the control of FIFO is mainly effective control of its read and write signals. FIFO writing is effectively controlled by the horizontal and vertical synchronization signals and pixel clock signals after CPLD image interception. After the FIFO writes a field of image data, the half-full signal is used as the interrupt signal of the DSP, and the image data is stored in the data space of the DSP through the interrupt service subroutine as the data source for recognition processing. The read control of the FIFO is realized by mapping it to the I/O space of the DSP. In order to distinguish it from other devices, the address lines A15 and A14 are used to participate in decoding. When the FIFO read signal is high, the data bus is in a high-impedance state, thereby achieving bus isolation.

 

　　4 Design of DSP storage space

　　DSP chips are widely used in various image processing systems due to their improved Harvard structure, fast processing speed, special DSP instructions and rapid implementation of various digital signal processing algorithms. In this system, TMS320VC5410 is selected as the central processor. The read and write cycle of this chip is 10ns and it has rich on-chip resources [2].

　　According to the size of the banknote number image and the requirements of the number recognition algorithm, this system has expanded a 64Kx16 RAM outside the DSP, in which the storage area of ​​0x0000-0x3fff is mapped to the program space of the DSP, and the storage area of ​​0x8000-0xffff is mapped to the data space of the DSP. . At the same time, a 256Kx16 FLASH chip SST39VF400A is externally expanded. According to the characteristics of DSP system program loading, the storage area with FLASH address 0x8000-0xffff is mapped to the DSP data space during the program downloading process, and is mapped to the DSP data space during the program loading process. The program space of DSP is controlled through the general-purpose I/O port XF of DSP. The storage areas of FLASH with addresses 0x0000-0x7fff, 0x10000-0x1ffff and 0x20000-0x2ffff are mapped to the program space of the DSP and used as record storage of the identified number results.

　　5 Use TL16C550 to realize communication with PC.

　　 During image acquisition and debugging and number algorithm debugging, in order to test the image effect, the image needs to be presented in the PC. Since the serial port of TMS320VC5410 is a synchronous serial port, but the communication with the PC is asynchronous serial transceiver, this article uses the asynchronous serial transceiver TL16C550 to realize the communication between the DSP and the PC. TL16C550 is a large-scale integrated circuit with asynchronous serial communication function produced by TI. The device is controlled through different configurations of the register selection input terminals A0, A1, and A2.

　　In this system, it is mapped to the address 0x8000 of the I/O space of the DSP, and the address lines A2, A1, and A0 of the DSP are connected to the register selection control pins A2, A1, and A0 of the 550, that is, through the I/O of the DSP. The O space address is 0x8000-0x8007 for register access. In TL16C550, the same interrupt signal INTRPT is used for reception and transmission. Different interrupts are enabled for data reception and transmission, and communication between the system and the PC is realized through interrupts.

　　6 system software design

　　Although manually written assembly language programs have the advantage of fast execution speed, writing programs in assembly language, especially programs for recognition algorithms, will be more time-consuming and laborious [4]. In order to improve the efficiency of program development, the C language of TMS320C54x is used for software development [5]. The software flow chart of the entire system is shown in Figure 6:

　　There are many algorithms for character recognition at present, including background feature point method, template matching method, structural feature analysis and judgment method, neural network recognition algorithm, etc. The structural feature analysis and judgment method starts from the structure of the characters themselves, detects the structural features of the numbers, and has the characteristics of rapid classification. According to the requirements of system speed, this article uses this recognition algorithm for the collected number images to complete the identification of banknote numbers. .

　　7Conclusion

　　This system uses TI's digital signal processor to collect banknote numbers, and Altera's complex programmable logic device CPLD to capture images. The image collection effect is very good. In addition to the functions of a general image processing system, this system is particularly suitable for dynamic image processing and has extremely high real-time performance.

　　References:

1. TMS320C54X DSP Reference Set, Volume 1:CPU and Peripherals, Texas Instruments, http://www.ti.com , 1999

2. TMS320VC5410 Data book, Texas Instruments, http://www.ti.com , 2000

3. Liu Jianye et al., Single-chip microcomputer implementation of banknote number reading and identification system, Industrial Control Computer, 2002, 15(1), 69-71

4. Zhang Qingfeng, Research on DSP-based banknote number identification system, Master's thesis of Harbin Institute of Technology , 2003

5. Liu Yicheng et al., TMS320C54X DSP application design and development, Beijing University of Aeronautics and Astronautics Press, 2002

6. Zhang Yong et al., C/C++ language hardware programming, Xi'an University of Electronic Science and Technology Press, 2003