In-depth understanding of the digital audio interface TDM in the software and hardware configuration issues

In the previous article "General Transmission Format of ADI Audio in PCBA", we introduced the transmission format of general audio in PCBA, which involves multiple formats. This article will select one of the most commonly used digital transmission formats for relevant analysis to help everyone understand how to design reasonably in software and hardware.

When designing audio in PCB boards, analog signals are often used as front and rear inputs and outputs, but the board is more dominated by digital signals. For example, we can see various aux, coaxial, lotus port and other signal inputs. As long as the audio needs to be processed, it generally needs to be converted into digital signals, such as when we are using FPGA, DSP, microcontroller and other systems. In most cases, the implementation of simple 2 channels is relatively simple in software and hardware, but when it rises to TDM8 or above, many customers will face stability issues. Next, it will be divided into two sections-software and hardware to explain how to effectively avoid these risks.

TDM software configuration notes

As mentioned above, TDM protocol generally has three wires (except MCLK), and some codecs have four wires. The main clock harness is generally a constant input, and the other three are BCLK, SYNC, and SDATA (DATA generally has DTX, DRX, or can be flexibly configured as DTX or DRX). How should the transmitter and receiver be configured to match them? The following will introduce them one by one:

♦ Determine how many channels of audio are transmitted

We need to select the TDM interface according to how many channels of audio are transmitted. Generally, there are TDM2/4/8/12/16/32. The specific selection needs to be based on the actual situation. Then determine the sampling rate and bit depth to obtain the exact bit clock data. For example, TDM16 uses a sampling rate of 48khz and a bit depth of 32bit, so the BCLK frequency determined is 16 * 48khz * 32bit = 24.576Mhz. In the driver, it is generally necessary to configure the specific TDM type, bit depth and sampling rate. The configuration here needs to be consistent between the transmitter and the receiver.

♦ Determine the type and polarity of SYNC

For the frame synchronization signal, its frequency is generally the sampling frequency. For example, in the TDM16 format, 16 channels of data can be transmitted within one cycle of the frame synchronization signal. At the same time, it has a pulse mode and a 50/50 duty cycle mode. The pulse mode starts with the first bit clock adding a pulse and ends at the end of the cycle. In the 50/50 duty cycle mode, the high and low levels occupy half of the channel respectively. For details, please refer to the sample diagram of the datasheet. It also has a polarity, that is, rising edge trigger or falling edge trigger. This part of the transmitter and the receiver also needs to be consistent.

♦ Determine the polarity of BCLK

In the first point, we have determined the approximate clock of BCLK, and the next step of polarity configuration is required. This polarity configuration actually corresponds to the SDATA bit, and it is necessary to distinguish between the driving edge and the sampling edge. In general, the driving edge configuration of the transmitter should be opposite to the sampling edge, and some formats should be the same. For details, please check the description of this content in the data manual.

In fact, even if the configuration is wrong, there will be sound output. Basically, experienced engineers can hear it, or analyze the data in the data array. The edges that do not correspond, the collected data is nothing more than overflow, or one bit is missing. When it is found that the 1khz sine wave enters, the collected data has this waveform feature, but there is no data in the high position, or no data in the low position, it sounds like the original sound is small and the noise is large. In fact, this is the reason. In addition, this configuration may be opposite or the same at the transmitter and the receiver, so it needs to be compared.

♦ Determine the format of the SDATA bit

The format mentioned here is closely related to the MSB and LSB in data transmission, which is for SYNC. At the beginning of the SYNC cycle, we can choose delay 1 or left-aligned and right-aligned formats. Here, strict alignment is required, otherwise the data will definitely be collected incorrectly. The configuration of the transmitter and the receiver needs to be consistent.

The above are basically some points to note in TDM software configuration. Of course, some chips may have added certain other functions based on these configurations, which requires specific reference to the corresponding datasheet. For example, ADAU1452 adds flexTDM function, AD2428's TDM adds delay 1 SYNC and offset, etc. The purpose of doing this is basically to improve the compatibility of the chip IP. Some manufacturers who do poorly may not be able to support TDM32 with their IP, and can only support TDM8, but in general, the above configuration instructions can cover these basic configurations.

TDM Hardware Design Considerations

Many people will say that TDM is just a few wires connected together? And IIS has never had any problems running? Most customers may have rarely designed signals above TDM8, and extreme cases rarely occur. This is because the audio interference environment of consumer electronics is less, but in automotive electronics, the external environment is more complex, and some unstable phenomena often occur. The following will focus on describing some problems and provide some solutions.

Why do we need to add resistors to the transmitter and receiver?

As shown in the figure below (Figure 1), we often add a resistor between IC1 and IC2. Many engineers actually don’t know why it is added and how big it should be? The following is a detailed explanation for everyone:

Figure 1 Schematic diagram of signal line connection

Usually we see that the audio chip connection line is generally connected with 0, 22, 33Ω resistors. In fact, the main purpose is to match the impedance, which involves the application of most of our high-frequency electronic circuits. Simply put, it is the internal resistance of the signal source, the characteristic impedance, and the load impedance. The best state is to achieve the same size of the three, and the phase of the transmitted signal is exactly the same. Of course, this is quite difficult. If the matching is not good and discontinuous, or when the signal frequency is too high, we will find that a lot of signal energy is lost, and the reflection is serious, and the waveform burrs are messy. The principle can be compared to the light being refracted and reflected at the same time when it is transmitted, so we should at least try to get closer to this direction.

When designing the TDM IP interface of the chip, the impedance of the transmitter is actually generally low, about 17-40Ω. The single-ended trace of the PCB is generally 50Ω, and the impedance of the receiving end is usually relatively large. This is a typical discontinuous and unmatched system, so we usually need to add a 22Ω resistor to the nearby transmitter, so that the impedance continuity problem can be basically maintained as a whole. Typical waveforms of mismatch are overshoot and ringing, as shown in the following figure (Figure 2). The risk of this problem is that it can easily lead to miscoding at the receiving end.

Figure 2 Typical waveform of mismatch between transmitter and receiver

Another situation is to absorb interference pulses. Sometimes we have very long traces, and then there are often some high-speed jump signals around the traces, especially those that are parallel and parallel. At this time, the signal line is very susceptible to interference, and there will be some burrs and narrow pulses, so it is difficult for our receiving end to judge, so it is easy to cause problems. For this type of problem, generally, the coupling is reduced by non-parallel traces, and a large resistor is added to the receiving end to absorb the energy of the narrowband pulse.

In general, the resistor on the signal line is mainly to match the impedance and reduce noise, while the current limiting and protection functions are basically less involved because the power is generally small.

Should bypass or decoupling capacitors be added to the transmitter and receiver?

Next, a real case will be used to illustrate. A customer has designed all the product requirements of the power amplifier and entered mass production, but after the product was installed on the car, it suddenly became silent at low temperatures or in some extreme conditions. After a long investigation, it was found that the core problem still occurred on the bypass capacitor of TDM.

Why add this capacitor? In automotive electronic products, we all have to pass the car regulations certification, which will cause a lot of engineers headaches: when the EMI and EMC level requirements are too high and cannot pass, engineers will consider adding some capacitors. On the one hand, because the bypass or decoupling grounding can consume a considerable part of the energy, the radiation is reduced. On the other hand, it can also reduce noise and improve electromagnetic compatibility.

In addition, in practical applications, we must pay attention to the problem of resonant frequency, especially the resonant frequency close to the signal frequency. After resonance, it is most likely to appear in the waveform jitter of the threshold of our signal, especially under some extreme conditions, the temperature drift property of the capacitor, combined with its own ESR, and the resistance in the circuit constitutes an RC filter circuit. If this problem occurs, it is basically caused by the inability to determine or misalignment of the TDM signal. Therefore, on this capacitor, those that do not need to pass strict certification generally do not need to be added, and those that need to pass certification should increase or reduce the capacity appropriately, especially when there is a hook back on the rising and falling edges, and this frequency is generally difficult to calculate. It is related to the transmission and reception, routing, and the ESR of the capacitor itself.

In short, you also need to be careful when adding capacitors and resistors, because if these conditions are not added well, the waveform quality will be affected. If the resistance is large, the waveform becomes a triangular wave, and if the capacitance is large, the waveform climbs into an arc, and the time of the rising and falling edges is greatly increased, which further affects the waveform quality.

In summary, as long as you pay a little attention to the two points introduced above and the layout design of the hardware, you can generally design a relatively stable product. Some customers have few problems because most of the IIS bandwidth is low enough and this situation rarely occurs. At the same time, the fault tolerance rate is relatively high, and the IP designed by the chip manufacturer is sufficient. This aspect also reflects that in the design, if TDM8 is sufficient, there is no need to use TDM16 or 32, because it will increase some unnecessary risks.