An article analyzing the HDMI spec transmission protocol

Publisher:TranquilDreamsLatest update time:2024-01-10 Source: elecfansKeywords:HDMI  spec Reading articles on mobile phones Scan QR code
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This article analyzes the HDMI spec from the perspective of a software engineer. The spec version is 1.4, which is also the most supported and mature version by most devices. The latest version is 2.0.


1 Overview

HDMI (High-Definition Multiface Interface) is an audio and video transmission protocol jointly released by Hitachi, Panasonic, Philips, SiliconImage, Sony, Thomson, and Toshiba. It is mainly used for the transmission of audio and video sources such as DVDs and set-top boxes to sink devices such as TVs and monitors. The transmission is based on the TMDS (Transition Minimized Differential Signaling) protocol. In addition, the use of TMDS is also a major feature of the DVI standard.

2 Physical Structure

o4YBAF9uJ66AJ8nwAAEIH6oEpqE809.jpg

The above figure is the HDMI block structure diagram. It can be seen that HDMI is used to connect audiovisual source and sink. HDMI cable has 3 sets of differential signals to transmit TMDS data and 1 set of differential signals to transmit clock. In addition, HDMI also has a DDC channel connected to the sink's EDID. CEC and HEAC are both optional protocols of HDMI.

pIYBAF9uJ7CACfkMAAEI8ywZ3vU070.jpg

HDMI defines five types of connectors, the picture above is the most common type A.
1-9 are pins used for TMDS data transmission, there are three groups;
10-12 are pins used for TMDS clock transmission, there is one group, TMDS clock is pixel clock;
13 is CEC pin, a transmission protocol compatible with consumer electronics;
14 is a reserved pin;
15,16 are DDC pins, DDC is based on I2C protocol transmission, so the pins are SCL and SDA;
17 is ground;
18 is +5V power;
19 is HPD pin, used to establish a connection.

3 Transmission

Overview

HDMI transmission consists of three groups of TMDS channels and one group of TMDS clock channels. The operating frequency of the TMDS clock is the pixel frequency of the video signal. In each cycle, each TMDS data channel sends 10 bits of data.

o4YBAF9uJ7KANEHwAAFfDG6L-As778.jpg

The figure above is a schematic diagram of HDMI transmission. It can be seen from the figure that HDMI transmits the following four types of data:
(1) Preamble control information, CTLx in the figure, can be used to indicate whether the following transmission is data island or video data. It is transmitted through D[1:0] of channel1 and 2, occupying 4 bits.
(2) Data Island, that is, data packet, such as Audio data packet. It is transmitted through D[3:0] of 3 channels, occupying 12 bits.
(3) Video Data, video data. The diagram transmits an RGB format image, R, G, B are transmitted through channels2, 1, and 0 respectively, each color is 8 bits, a total of 24 bits.
(4) HSYNC, VSYNC. It is transmitted using D[1:0] of channel0, occupying 2 bits.
The 8-bit data is converted into 10-bit data after passing through the TMDS encoder at the source, and is serially output after passing through the serializer; it is first restored to 10-bit data at the sink end, and then the 8-bit source data is obtained through the TMDS decoder.
In addition, HDMI video is transmitted in stream mode, and does not involve packet mode transmission.

o4YBAF9uJ7SAOzN4AACtqzXYuns208.jpg

The above figure is the HDMI timing diagram for transmitting 720x480p video.
In the video data period, valid video data is transmitted;
in the data island period, audio and auxiliary data are transmitted in the form of packets;
in the control period, CTLx and HSYNC, SYNC are transmitted.
Both the data island period and the control period are performed in the blanking area. In the figure, the line blanking occupies 138 pixels and the field blanking occupies 45 lines.

pIYBAF9uJ7WAG7kZAABqw4W2kFM940.jpg

The figure above illustrates the data and encoding types transmitted in the three periods described in the timing diagram. Video data is encoded from 8bit/channel to 10bit/channel, data island packet data is encoded from 4bit/channel to 10bit/channel, and control data is encoded from 2bit/channel to 10bit/channel.

Control Period

o4YBAF9uJ7aAVhZTAACRc-Uie_c589.jpg

There are only two types of preamble information combinations. CTL0:3=1000 means the next period is the video data period, and CTL0:3=1010 means the next period is the data island period. HSYNC and VSYNC may also change at this time.

Video Data Period

The video data period starts with a leading gray band of 2 pixels in length. The guard band is as follows:
ch0: q_out[9:0] = 0b1011001100
ch1: q_out[9:0] = 0b0100110011
ch2: q_out[9:0] = 0b1011001100

Data Island Period

The data island period transmits audio data and auxiliary data. The auxiliary data includes Infoframe and other data used to describe audio and video information. The data island period starts with a leading guard band of 2 characters and ends with a trailing guard band of 2 characters. The guard bands are as follows:
ch0: q_out[9:0] = na
ch1: q_out[9:0] = 0b0100110011
ch2: q_out[9:0] = 0b0100110011
For details on the packet type and format of data island transmission, see the spec description.

The transition process of the three transmission stages is shown in the following figure:

pIYBAF9uJ7mAIZQpAAIDWKeXjd4475.jpg

(1) The left one is the control period, which occupies three channels D[1:0], channel 0 transmits HSYNC, VSYNC, channel 1,2 transmits Preamble
(2) The left two is the data island period, which occupies three channels D[3:0], channel 0 D[1:0] transmits HSYNC, VSYNC, channel 0 D[3:2] transmits packet header, channel 1,2 D[3:0] transmits packet. Both ends are isolated by guard band
(3) The right two is the control period again
(4) The right one is the video data island, which occupies all three channels and starts to be isolated by guard band

4 Video

Supports three pixel encodings: RGB4:4:4, YCbCr4:4:4, YCbCr4:2:2
video format. In addition to the CEA-861-D format, it also supports some special formats.
The color depth can support 24, 30, 36 and 48 bits per pixel.
The following are the pixel encoding diagrams of 24bit/pixel RGB444, YCbCr422, and YCbCr444. Each color of RGB444 occupies 8 bits, Y occupies 12 bits for YCbCr422, and 12 bits for C, and Y, Cb, and Cr all occupy 8 bits in YCbCr444.

o4YBAF9uJ7uAfBrqAADXqmUhBFo316.jpg


pIYBAF9uJ7yAUiVeAAEUf_bGzZc682.jpg


pIYBAF9uJ76AHR9hAACwUbKyUAM370.jpg

Deep Color mode
Pixel Packing
24 bit mode: 1 pixel/group, 1 fragment/group
30 bit mode: 4 pixel/group, 5 fragment/group
36 bit mode: 2 pixel/group, 3 fragment/group
48 bit mode: 1 pixel/group, 2 fragment/group
1fragment/TMDS clock, such as 4 pixels at 30 bits, it takes 5 transmissions to complete, 1 fragment each time.

o4YBAF9uJ8CAN9lZAAFCWCxQnn4434.jpg

5 Audio
Audio data is transmitted in the form of Audio Sample Packet or High Bitrate Audio Stream Packet, but HDMI does not transmit audio clock, so the sink device needs to perform audio clock regeneration. The principle is as follows:

pIYBAF9uJ8GAeEdbAADpRKt5vh8128.jpg

128∗fs=N×fTMDS/CTS
N and CTS will be transmitted in the Audio Clock Regeneration Packet. The TMDS clock can be obtained through hardware, so the sink end can calculate the audio clock transmitted by the source.

6 Control

InfoFrame

Infoframe is transmitted in the form of Infoframe packet, and its size does not exceed 30 bytes plus a checksum byte. The specific format and content of the infoframe need to be checked in the spec.
AVI (Auxiliary Video Information) Infoframe
Audio Infoframe
HDMI Vendor Specific Infoframe, this packet needs to be sent when transmitting 4kx2k or 3D format

EDID & DDC

The sink device stores EDID information in ROM. After receiving HPD, the source reads EDID through the DDC channel to obtain the properties of the display device. EDID consists of two parts. The first 128 bytes conform to the EDID1.3 data structure, and the 128-byte extended EDID conforms to CEA extension verison3. CEA extension verison3 is shown in the figure below.

pIYBAF9uJ8WAVeyrAAM5BBKFbpI518.jpg

HDMI VSDB

The HDMI sink device contains HDMI VSDB in the first extended EDID. After reading the EDID, the source will determine whether the device is HDMI or DVI based on whether this block exists.

Hotplug

The source will monitor the status of the HPD pin. When the source and sink are connected, if the HPD is high, it means that the sink device is working normally and the source can read the EDID through DDC. If it is low, it means that the sink is disconnected.
The sink can pull down the HPD for more than 100ms to indicate to the source that the EDID has changed. At this time, the source will re-read the EDID.

HDCP

There is a lot of content involved, which will be explained in a separate chapter.


Keywords:HDMI  spec Reference address:An article analyzing the HDMI spec transmission protocol

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