It should be noted that the dead time of the control switch when the switches on the same pin are actuated simultaneously, which only occurs when the current is close to zero. Above and below a certain safety margin (FOC parameter i_margin), only one switch in a pair of switches is actively controlled.

5. Level 4

Level 4 abstract template is the bottom layer of the schematic diagram, with detailed inverter circuit. However, the simulation speed is the slowest. The simulation speed of this layer is 1/20 of the upper layer simulation speed. The inverter characteristics are built using the IGBT tool based on the Infineon IGBT datasheet.

Level 4 FOC control is implemented using C language, but the implementation function is the same as Level 3 mast language.

Level 4, the inverter is built using actual components, the FOC algorithm uses a C compiler, and the C file name is pmsm.c. Its implementation principle is exactly the same as that of Level 3.

5.1 Foc module

From the foc model description, we can see that the architecture is the same as that of Level 3, except that the algorithm calls the foc_pmsm.c file.

5.2 Inverter

Figure 11 Inverter and its parameter settings

Figure 12 Inverter model macro circuit

Figure 13 IGBT controller model macro circuit

6. Summary

This article introduces the trade-off between simulation accuracy and simulation speed in different stages of motor design, involving four modeling methods. Their characteristics are shown in the following table:

• The DP model provides the highest simulation speed and can be used to efficiently perform cycle simulations. This model can be used to evaluate overall efficiency, evaluate load balancing, evaluate motor management strategies, and analyze long-term operating thermal simulations.

• The averaged PWM model is suitable for motor control (FOC or DTC) optimization and analysis of drive dynamics, including torque pulses and vibrations introduced by motor imperfections.

• Deal switch models are suitable for evaluating PWM schemes (such as sinusoidal or space vector) and fault protection strategies (fuses, redundant inverters, etc.)

• Detailed semiconductor models are suitable for evaluating inverter stresses (maximum dI/dt and dV/dt, voltage and current spikes) and for designing gate-drive circuits with optimal switching speeds and dead times. Models at this level generate device loss tables that are used by upper-level modules.