Music player experiment based on I2S interface of MM32F0163D7P-EEWORLD

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I2S (Inter-IC Sound) bus, also known as the integrated circuit built-in audio bus, is a bus standard developed by Philips for audio data transmission between digital audio devices. It uses independent wires to transmit clock and data signals, and avoids distortion caused by time difference by separating data and clock signals.

The I2S interface of the MM32F0160 series has the following main features:

Half-duplex communication (transmitter or receiver only)
Master or slave operation
9-bit configurable linear prescaler to achieve accurate audio sampling frequency (8KHz~192KHz)
Data frame format can be configured as 16-bit, 24-bit or 32-bit
The data packet frame is fixed to 16 bits (16 bits of valid data) or 32 bits (16 bits, 24 bits, 32 bits of valid data)
Configurable clock polarity (steady state)
Underflow flag in transmit mode (slave only), overflow flag in receive mode (master/slave), and frame error flag in transmit/receive mode (slave only)
32-bit registers for transmit and receive are time-division multiplexed for two channels
Data direction is always MSB first
Support I2S protocol:

Philips Standard
MSB justification (MSB bit aligned to the left)
LSB justification (LSB bit is aligned to the right)
PCM standard (with two modes: short frame synchronization mode and long frame synchronization mode)

Transferring data using DMA requests (32 bits wide)
Configurable MCLK clock output to drive external audio components, with a fixed ratio of 256×Fs (where Fs is the audio sampling frequency)

1. Brief description of MM32's I2S bus

The I2S bus and SPI bus of MM32F0160 are multiplexed, namely SPI_I2S serial peripheral (serial peripheral interface and integrated circuit built-in audio bus).

The pin multiplexing relationship between the I2S bus interface and the SPI bus interface is as follows:

SD: Serial Data (mapped on MOSI pin), used to send or receive two multiplexed data channels (only in half-duplex mode).

WS: Channel Select (mapped on the NSS pin), which is the output signal of the control data in master mode, or the input in slave mode.

CK: Serial Clock (mapped on the SCK pin), which is the output of the master mode serial clock or the input of the slave mode serial clock.

MCK: Optional serial clock (mapped on MISO pin) used to drive external audio components (only used if external audio device requires clock input, provided by master mode).

2. SPI_I2S Functional Block Diagram Introduction

Figure 1 SPI_I2S functional block diagram

As shown in Figure 1 above, this is the functional block diagram of the SPI_I2S peripheral. The SPI_I2S is mounted on the APB and DMA buses through the "bus interface logic", TXREG and RXREG registers, master mode control unit and slave mode control unit, master-slave selection control, transceiver control logic, and clock generation and control unit, 8Byte transmit buffer and 8Byte receive buffer, and the clock control unit is provided with clock by Spbrg and Pclk.

3. I2S clock prescaler for SPI_I2S peripheral

The I2SCLK clock is provided by the system APB clock. The prescaler circuit structure of the I2S module is shown in Figure 2 below:

Figure 2 SPI_I2S clock prescaler circuit diagram

As shown in Figure 2 above, when the MCKOE bit is '0', the chip does not need to output the MCK clock, and the prescaler directly divides the I2SCLK to CK; when the MCKOE bit is '1', the chip will output the MCK clock, and the prescaler divides the I2SCLK to obtain MCK, and then further divides it to obtain CK (the division multiple is selected by CHLEN as 4 or 8).

The audio sampling rates are usually 192KHz, 96KHz, 48KHz, 44.1KHz, 32KHz, 22.05KHz, 16KHz, 11.025KHz, 8KHz. Therefore, the desired audio sampling rate can be obtained by configuring the I2SDIV[8:0], MCKOE and CHLEN bits in the I2SCFGR register according to the circuit function pattern of the I2S clock divider.

When I2S transmits data, the bit rate calculation formula is shown in Table 1 below (one clock cycle output by CK corresponds to the transmission of 1 bit of data, so the bit rate = CK frequency FCK).

Table 1

The relationship between the audio sampling rate (Fs) and the I2S bit rate is defined by the following formula:

Fs = I2S bit rate / (channel length × number of channels) = FCK / (channel length × number of channels)

Note: Channel length, i.e., data packet frame length, can be configured as 16 bits or 32 bits; the number of channels refers to the left and right channels, and the value is fixed at 2.

In summary, according to the configuration of I2SDIV[8: 0], MCKOE and CHLEN bits, the relationship between the audio sampling rate and FI2SCLK (APB clock frequency) is shown in Table 2 below:

Table 2

4. SPI_I2S peripheral I2S interface music player

Working Principle

The working principle block diagram of the music player based on the I2S interface is shown in Figure 3:

Figure 3 Schematic diagram of a music player with I2S interface

As shown in Figure 3 above, this is the working principle block diagram of the music player with I2S interface:

The MM32F0160 is used as the host MCU and its SPI1 interface is used to drive the 25WQ80 memory to write and read the stored audio files.

The I2S2 (SPI2_I2S2) interface on the MCU side works in slave mode, and MCLK does not output the clock. Through PWM, the 12MHz REF_Clock is output to the MCLK pin of the NAU88C22 audio codec chip. The NAU88C22 internal PLL synthesizes a stable 12.288MHz as the internal IMLCK master clock. The NAU88C22 BCLK outputs the bit clock clock to the MCU side I2S2_CK as the audio sampling clock. The I2S2_WS interface, i.e. FS, is used to switch the left and right channels in time. The I2S2_SD interface, i.e. DACIN, outputs the audio signal stream DAC Stream read from the 25WQ80 memory and transmits it to the NAU88C22 audio codec chip.

The I2C_SDA and I2C_SCL interfaces on the MCU are used to set the NAU88C22 operating mode and parameters. The NAU88C22 DAC output can be selected to drive the speaker from the Speaker PA output or drive the earphone from the Earphone PA headphone interface.

5. GPIO initialization of I2S interface

The initialization code of the I2S interface GPIO is as follows:

void I2S2_GPIO_Init(void)

{

GPIO_InitTypeDef GPIO_InitStruct;

RCC_GPIO_ClockCmd(GPIOB, ENABLE);

GPIO_StructInit(&GPIO_InitStruct);

/* PB12 I2S2_WS */

GPIO_InitStruct.GPIO_Pin = GPIO_Pin_12;

GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_Init(GPIOB, &GPIO_InitStruct);

/* PB13 I2S2_CK */

GPIO_InitStruct.GPIO_Pin = GPIO_Pin_13;

GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_Init(GPIOB, &GPIO_InitStruct);

/* PB14 I2S2_MCLK */

GPIO_InitStruct.GPIO_Pin = GPIO_Pin_14;

GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;

GPIO_Init(GPIOB, &GPIO_InitStruct);

/* PB15 I2S2_SD */

GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15;

GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_Init(GPIOB, &GPIO_InitStruct);

/* PB12 OF I2S2_WS */

GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_0);

/* PB12 OF I2S2_CK */

GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_0);

/* PB12 OF I2S2_MCLK */

GPIO_PinAFConfig(GPIOB, GPIO_PinSource14, GPIO_AF_0);

/* PB12 OF I2S2_SD */

GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_0);

}

6. Initialization of I2S slave

The initialization steps of the I2S slave are as follows:

Configure the SPI_I2S_GCTL.SPIEN bit to '1' to enable the module;

Configure the SPI_I2S_GCTL.MODE bit to '0' to make the module function as slave mode;

Configure the I2SDIV[8:0], DATLEN and CHLEN bits in the SPI_I2S_I2SCFGR register to match the desired audio sampling frequency and data packet frame format;

Configure the SPI_I2S_I2SCFGR.SPI_I2S bit to '1' to enable the I2S transmission function;

Configure the I2SSTD[1: 0] and PCMSYNC bits in the SPI_I2S_I2SCFGR register to select the communication standard used for I2S transmission;

Configure the SPI_I2S_GCTL.DMAMODE bit to '1' to enable DMA transfer;

Enable half-duplex transmission permission, that is, configure the TXEN or RXEN bit in the SPI_I2S_GCTL register to '1' (TXEN and RXEN cannot be configured to '1' at the same time).

Note: When sending in slave mode, before detecting the edge of WS, it is necessary to write data to the register SPI_I2S_TXREG once; and when receiving in slave mode, it is necessary to keep the WS input signal at a high level before configuring the RXEN bit to '1'.

The initialization code of the I2S slave is as follows:

void I2S2_Slave_Init(void)

{

RCC_APB1PeriphClockCmd(RCC_APB1ENR_SPI2, ENABLE); /* Enable SPI2_I2S Clock */

SPI2- >CCTL &= ~SPI_CCTL_LSBFE; /* MSB first enable */

SPI2- >CCTL &= ~SPI_CCTL_CPHA; /* Clock phase select start second clock */

SPI2- >CCTL |= SPI_CCTL_CPHASEL; /* CPHA polarity select start second clock */

SPI2- >CCTL |= SPI_CCTL_SPILEN; /* SPI character length 8bit data */

SPI2- >CCTL |= SPI_CCTL_CPOL; /* Clock polarity select high */

SPI2- >CCTL |= SPI_CCTL_TXEDGE; /* Transmit data edge for i2s bus */

SPI2- >I2SCFGR &= ~SPI_I2SCFGR_MCKOE; /* I2S master clock output disable */

SPI2- >I2SCFGR &= ~SPI_I2SCFGR_CHLEN; /* Vocal tract length 16bit */