Power management and power consumption allocation of intelligent driving systems

When designing the architecture of a high-level autonomous driving system, the architecture inside the domain control usually involves the main control chip MCU, computing chip SOC, power management module chip PMIC, serializer and deserializer, CAN transceiver, network switch, etc. These design elements mentioned are not just a simple hardware connection and wiring to a certain extent at the bottom level, but from a software perspective, the network configuration, power management, storage configuration, etc. of the related systems involved all require the simultaneous development of corresponding software and hardware modules. Among them, power configuration and network startup configuration, as two relatively important high-level domain control configuration units, have always been part of the design content that system architects, hardware architects, and software architects need to overcome.

This article will take a typical system architecture formed by a popular power management chip PMIC as an example to provide a detailed description of power management and network management for the power management solution. It includes a power distribution network (PDN) between two power management module PMICs (typically TPS6594-Q1 devices) and a DRA829V (TI's DRA829V is a dual Arm Cortex-A72, quad-core Cortex-R5F, 8-port Ethernet and 4-port PCIe switch) or TDA4VM (intelligent driving domain control SOC processor) with independent MCU and main power rails.

The TDA4 series chip can be used as a classic low-level version of a super-heterogeneous chip, and its corresponding internal processor can be used as an independent safety monitor (MCU safety island) resource for the main processing, which is required to ensure the safe operation of the system. The MCU processor needs to maintain minimal system control capabilities (also known as MCU Only mode) to significantly reduce processor power consumption, thereby extending battery life during standby use cases and reducing component temperature.

1. Power management profiles for different intelligent driving system architectures

Of course, the use degree and scenarios of intelligent driving system chips in the industry vary according to their application requirements. As a primary version of the super-heterogeneous chip, in general, the L2 level requires 5 TOPS of computing power, the L3 requires 100+ TOPS of computing power, and the L4 is 300+ TOPS. Therefore, low-level driving assistance systems (L0~L2) usually use a single chip such as TDA4VM (8Tops+25KDMIPs) to meet the overall demand for computing power. However, the processing power of chips such as the second-highest level (L2+~L4) seems to be a bit inadequate. Considering that the current focus of research and development in the entire industry tends to be on systems such as L2+. Therefore, the power distribution management solution introduced in this article mainly considers the situation of multiple SOCs, such as the typical TDA4 VH, 8650, etc. for architectural description.

The following figure shows the difference in power control logic between pure heterogeneous chip architecture and hyper-heterogeneous chip.

From the perspective of domain control architecture design, hyper-heterogeneous chips often concentrate all computing resources on one chip, and this chip basically drives and controls the power supply of all related chips in the intelligent driving domain control (such as adders and deserializers, switches, Can transceivers, and camera control terminals). Therefore, we usually call this type of control connection series control, that is, the power control link is usually managed by a unified PMIC for the central chip. Of course, if the low power consumption of the architecture is taken into account, the PMIC of the central control chip may also be split into master and slave paths for separate control. The main path implements power control management under full power consumption. The slave path implements separate power management when the user needs to reduce power consumption (for example, only activating the internal MCU Only module through the PMIC link setting).

As for the pure heterogeneous chip intelligent driving domain control architecture, when designing the power tree, the single-chip single-control method is usually referred to. For example, if the three types of chips, MCU, SOC, and GPU, are integrated into the same system architecture, a separate power control method is usually adopted, that is, the power supply of each chip is individually controlled. The power on and off control of chips such as adders and deserializers and CAN transceivers is equipped with a separate power control module according to user customization requirements. For example, consider power control for the wake-up CAN separately, or power control for the bypass image output control separately. Chips such as Switch can be opened and closed by MCU alone.

2. Basic power tree design of intelligent driving system

The following figure shows the power tree structure of the intelligent driving system that will be introduced in detail in this article. The front-end power supply of the power tree is provided by the vehicle power battery. Considering the huge power consumption of the intelligent driving system, usually, the power supply adopts a high-voltage large battery power supply mode. Of course, in some special cases, it can also be switched to a small battery power supply (such as the sentinel mode that is activated within a certain period of time after power-off, or the long-endurance mode activated by new energy vehicles in the later stage of driving). In addition, there are different wake-up methods for power wake-up (ACC gear is directly powered on through IG ON, CAN network wake-up message injection, or other mechanisms that consider the need to wake up the chip separately).

The initial DCDC step-down conversion involved in the entire power-on management process generally converts the 12V battery power supply into a lower voltage according to demand, such as 5V, 3.3V and other voltage values ​​for use by different chips. For example, TDA4 requires 3.3V power supply, and other chips require 5V power supply. Then, after the initial voltage transformation of the PMIC power management module, the main computing chip of the intelligent driving system can be directly powered by voltage distribution control. Of course, there are also some chips (such as adder and deserializer 1.0V-1.8V, CAN transceiver 5V, Ethernet Switch 1.0V-3.3V, etc.) that need to be processed Post DCDC according to their own needs after the initial step-down configuration. In addition, there will be mutual dependence between the startup and data processing of the intelligent driving system. Usually, depending on the different data sources it processes, the central computing chip SOC/MCU will be considered as the control enable end for the remaining chips. For example, if the SOC is used to process the data of the visual perception input source, then it is necessary to set a control connection line (such as an IIC line) between the SOC and the adder/deserializer and the Power Switch that directly powers the directly connected camera as an enable line adjustment. In addition, if the MCU is used as the data processing terminal of the millimeter-wave radar (for trajectory planning), it controls the central task of inputting and processing the millimeter-wave radar data. The enablement and power control of the corresponding Can transceiver can be directly controlled by the MCU of the intelligent driving domain control or directly connected to the vehicle's normal power.

The entire power tree design process requires reverse voltage design, wake-up response design, voltage regulation design/voltage transformation design (DCDC, LDO, PMIC), power switch design, etc. The following lists several typical chip selections and corresponding feature parameter descriptions.

1) LDO (MPQ20051): Low dropout linear regulator that can provide up to 1A of current and 140mV of voltage. When the input voltage is 2.5V to 5.5V, its corresponding adjusted output voltage range is from 0.8V to 5V. The internal PMOS pass element allows a low ground current of 130uA, making the MPQ20051 suitable for battery-powered devices. Other features include low-power shutdown, short-circuit and thermal protection.

2) DCDC (MAX20074ATBA/V+): represents a step-down switching regulator IC. The lowest automotive synchronous buck controller, using only 3.5µA of quiescent current at light load.

3) DCDC (MPQ2166): It is an internally compensated, dual-channel, PWM, synchronous, step-down regulator that can operate from an input voltage of 2.7V to 6V and produce an output voltage as low as 0.6V. The MPQ2166 can be configured as a 2A/2A or 3A/1A output current regulator, with a quiescent current as low as 60µA. The MPQ2166 has peak current mode control and internal compensation, and is capable of low dropout configuration. Both channels can operate at 100% duty cycle, and full protection features include cycle-by-cycle current limiting and thermal shutdown.

4) PowerSwitch (MAX20086–MAX20089): Dual/quad camera power protector ICs provide up to 600mA of load current to each of its four output channels.

As for PMIC chips, the following types are mainly used here to achieve different power management controls.

5) PMIC (PF71): This is a power management integrated circuit designed for high-performance i.MX 8 processors. It has five high-efficiency step-down converters and two linear regulators to power the processor, memory, and other peripherals. Built-in one-time programmable memory stores key startup configurations, greatly reducing the external components typically used to set the output voltage and external regulator sequence. The regulator parameters can be adjusted through high-speed I2C after startup, providing flexibility for different system states.