Mir ARM+FPGA architecture development board PCIE2SCREEN example analysis and test

Mir ARM+FPGA architecture development board PCIE2SCREEN example analysis and test

This test content is the ARM+FPGA architecture-based Mir MYD-JX8MMA7 development board, and its ARM-side test routine pcie2screen, and introduces the modification of the FPGA-side program.

01. Test routine pcie2screen

The pcie2screen example is a test example for the MYIR_PCIE_5T_CMOS project of the MYD-JX8MMA7 development board. It is used to display the video captured by the camera connected to the FPGA. After running the program, a window titled demo will be displayed on the screen.

Use the mouse to click the ready button, and the demo window will display continuous video, indicating that the camera, DDR, and PCIE interface are all normal. If there is no camera connected, the program will display a messy image.

The source code of this test case is not included in the SDK, but can be obtained from the technicians of Mir Corporation. This example program is developed with Qt and uses OpenGL technology. The program includes the following main classes:

• MainWindow: QMainWindow subclass, which is the display window.

• uOpenglYuv: QOpenGLWidget subclass, used to display the captured image. The initializeGL function of this class is used to initialize OpenGL. The paintGL function is used to draw the image, and the core statement is:

glTexImage2D(GL_TEXTURE_2D, 0, GL_RGBA, vW, vH, 0, GL_RGBA, GL_UNSIGNED_BYTE, pRGB);

pRGB stores the data read from the FPGA. From this sentence we can see the format of the image required by the program.

• xdma_getImg: main thread class

• xdma_programe: encapsulates the RIFFA interface, in which read_pack is used to read FPGA data and is called cyclically by the main thread. Its function definition is as follows:

int xdma_programe::read_pack(char *pData, int len)

{

//int buffer[1920 * 1080];

//int buffer[1024 * 768];

int buffer[1280 * 720];

int i;

if(dev_fd != NULL)

{

fpga_send(dev_fd, 0, buffer, len / 4, 0, 1, 25000);

fpga_recv(dev_fd, 0, buffer, len / 4, 25000);

memcpy(pData, (char *)buffer, len);

return len;

}

else

{

return 0;

}

}

It can be seen from the function that before each data read, the function first writes data to the FPGA (the data is meaningless and is related to the FPGA's state machine), and reads in a whole frame of data each time.

02. Modification of FPGA-side program

The logic control of the FPGA side is in chnl_tester.v, which defines a state machine for controlling data transmission and reception. The state machine is defined as follows:

always @(posedge CLK or posedge RST) begin

if (RST) begin

rLen <= #1 0;

rCount <= #1 0;

rState <= #1 0;

rData <= #1 0;

vout_vs_r <= #1 0;

end

else begin

case (rState)

3'd0: begin // Wait for start of RX, save length

if (CHNL_RX) begin

rLen <= #1 CHNL_RX_LEN;

rCount <= #1 0;

rState <= #1 3'd1;

end

end

3'd1: begin // Wait for last data in RX, save value

if (CHNL_RX_DATA_VALID) begin

rData <= #1 CHNL_RX_DATA;

rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);

end

if (rCount >= rLen) begin

rState <= #1 3'd2;

end

end

3'd2: begin // Prepare for TX

if (read_valid) begin

rCount <= #1 0;

rState <= #1 3'd3;

end

end

3'd3: begin // Start TX with save length and data value

if (CHNL_TX_DATA_REN) begin

//rData <= #1 data_in;

rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);

if (rCount >= rLen)

rState <= #1 3'd4;

end

end

3'd4: begin

if (vout_vs_r)

rState <= #1 3'd5;

else begin

vout_vs_r <= #1 1;

rState <= #1 3'd4;

rCount <= #1 0;

end

end

3'd5: begin

if (vs_flag) begin

rState <= #1 3'd0;

vout_vs_r <= #1 0;

end

else

rState <= #1 3'd5;

end

endcase

end

end

We don't have a camera to test with, so we simply modify the program to send a blue gradient band signal.

The core modifications are as follows:

…

reg [31:0] rColor = 0;

…

assign CHNL_TX_DATA = (read_en)? {rColor, rColor}:64'd0;

…

3'd3: begin // Start TX with save length and data value

if (CHNL_TX_DATA_REN) begin

//rData <= #1 data_in;

// if (rCount % 5 == 4)

rColor <= #1 rColor + 1;

if(rColor >= 255)

rColor <= #1 0;

rCount <= #1 rCount + (C_PCI_DATA_WIDTH/32);

if (rCount >= rLen)

rState <= #1 3'd4;

end

end

…

03. Test results

We did not modify the test program on the ARM side, and still used the pcie2screen provided by the manufacturer, but re-burned the FPGA program. The program's running effect is as follows:

Mir MYC-JX8MMA7 core board and development board.

Mier MYC-JX8MMA7 core board and development board adopt ARM+FPGA processing architecture, NXP i.MX8M Mini and Xilinx Artix-7 processors, quad-core Cortex-A53, Cortex-M4, Artix-7 CPU, 1.8GHz main frequency, based on ARM+FPGA processing architecture, with high performance, low cost, low power consumption and other characteristics, both of which have their own functions and play the unique advantages of the original architecture. The Artix-7 CPU equipped with Zynq 7010 FPGA resources can meet the needs of high-speed data acquisition, and uses PCIE high-speed communication to support 200~300MB/S communication capabilities. It can provide excellent video and audio experience, combining the specific functions of the media with high-performance processing optimized for low power consumption, and has 1080p 60Hz H.265 and VP9 decoders to meet the requirements of high-definition display.

In order to facilitate developers' research and evaluation, Mir provides the matching MYD-JX8MMA7 development board, which is powered by 12V/2A DC and equipped with 1 Gigabit Ethernet interface, 2 SFP optical module interfaces, 1 USB2.0 protocol M.2 B-type socket 5G module interface, 1 SDIO/serial port protocol WIFI/Bluetooth interface, 1 HDMI display interface, 1 LVDS display interface, 1 MIPI CSI interface, 1 DVP camera interface, 1 audio input and output interface, 2 USB HOST Type A, 1 USB Type-C, 2 Micro SD, 1 FMC expansion interface, and 1 Raspberry Pi compatible expansion module interface.

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