Design and implementation of digital communication signal generator based on ADSP-BF533

0 Introduction

In the study of communication confrontation, in order to simulate the real digital communication signal scene, the digital communication signal generator is an indispensable instrument. However, the communication signal generator on the market is very expensive and has relatively simple functions. Moreover, the output code element of this type of communication signal generator is uncontrollable, and the signal-to-noise ratio and interference-to-signal ratio cannot be dynamically adjusted. Therefore, it is impossible to simulate the mixed environment of communication signals of various modulation types, and it is extremely inconvenient to use it as a performance test signal source for communication confrontation systems. Therefore, it is of great theoretical significance and practical value to carry out research on the reconstruction method of high-precision communication signals and noise interference waveforms.

1 Introduction to ADSP-BF533 Chip

ADSP-BF533 is a medium-to-high-performance product of the Blackfin series, specifically for various applications in multimedia (especially video processing) and communications. It contains 2 multiplier/accumulators (MACs), 2 40-bit ALUs, 4 video ALUs and 1 40-bit shifter. The BF533 core operating clock can be as high as 600 MHz. The arithmetic unit processes 8-bit, 16-bit or 32-bit data from the register group.

Each MAC of BF533 can complete a 16-bit by 16-bit multiplication operation per cycle, and can accumulate the result into a 40-bit accumulator, while providing 8-bit precision extension. Its ALU unit performs standard arithmetic and logic operations, and the two ALUs can process 16 or 32-bit data. The operation unit has great flexibility. Therefore, it can meet the requirements of signal processing in various applications.

ADSP-BF533 regards the memory as a unified 4GBytes address space. All resources, including internal memory, external memory and I/O control registers, occupy corresponding parts of the public address space and are independent of each other. The various parts of the memory in this address space are arranged in a hierarchical structure to provide high performance and price ratio. High-speed, low-latency, small-capacity memory (such as CACHE or SRAM) is located very close to the processor, while low-speed, high-latency, large-capacity, low-cost memory (such as SDRAM or Flash) is far away from the processor.

The L1 memory in BF533 is the most important memory with the highest performance in the core; L2 memory is used to provide additional storage capacity and has lower performance: the off-chip storage system is accessed through the external bus interface unit (EBIU); the asynchronous memory unit can connect to 4 asynchronous memory banks or IO interfaces, and each bank can support a maximum of 1MBytes of physical addressing space; the synchronous memory unit can be expanded by SDRAM and can access up to 128MBytes of physical storage space; the memory DMA controller provides high-bandwidth data transfer capabilities and can complete block transfers of code or data between internal L1/L2 memory and external memory space.

In addition, ADSP-BF533 also provides a parallel interface (PPI) that can be directly connected to parallel A/D and D/A converters, video encoders and decoders that comply with the ITU-656 standard, and other general peripherals. The PPI includes a dedicated clock pin, up to 3 frame synchronization pins, and up to 16 data pins. The general mode of PPI is divided into 4 main working modes, namely: data reception of internally generated frame synchronization signals, data reception of externally generated frame synchronization signals, data transmission of internally generated frame synchronization signals, and data transmission of externally generated frame synchronization signals. Each PPI_CLK clock cycle can transmit up to 16 bits of data, which is widely used in various data acquisition and data transmission occasions.

2 System Hardware Design

The digital communication signal generator system is divided into two modules: microcomputer module and waveform generation module. The microcomputer is a general-purpose computer or PC, and the waveform generation module is a designed signal generation board. Figure 1 shows the overall block diagram of the system.

The general microcomputer first generates various types of digital modulation signals, Gaussian narrowband white noise and various types of interference signals according to the parameters input by the user, and then transmits the data to the signal generation board through the USB interface. The signal generation board then cyclically takes out the data in the communication waveform memory and the interference/noise memory through the waveform generation controller, and finally generates a continuous digital communication signal waveform through the DAC. Figure 2 shows the block diagram of the system hardware design.

DSP1 in the hardware design is the core of the entire system, which can communicate directly with the microcomputer and control the loading and operation of DSP2. The loading mode of DSP1 is BMODE 01 mode, which is loaded from the external Flash; DSP2 is BMODE 10 mode, which is loaded through the SlaveSPI interface.

DSP1 first receives the waveform data packet transmitted by the microcomputer through the USB interface, and transmits the communication waveform or communication environment waveform data in the data packet to the communication/communication signal environment waveform data memory (SDRAM1) in MDMA mode. At the same time, the noise data is transmitted to the internal RAM of DSP2 in SPI MDA mode, and then after DSP2 receives it, the noise/interference data is stored in the noise/interference data storage segment (SDRAM2) in MDMA mode. DSP1 transmits the signal-to-noise ratio/interference-to-signal ratio parameters to the internal RAM of DSP2 through SPI non-DMA. The high bit of the communication data (D15) is the baseband code stream data, and D14 is the synchronization signal used to test the baseband code stream.

In the system, the sampling frequency of all waveform parameters is 10MHz, the data capacity is 16M×16 bits, and 1.5 seconds of waveform data can be stored. The number of valid data bits is 14 bits. DSP1 directly reads the communication waveform data from SDRAM1 in a loop through PPIDMA and transmits it to DAC1 to generate a communication waveform. DSP2 uses the program to generate a random address to obtain the starting address of MDAM0, and then reads the stored noise waveform data from SDRAM2 into the internal RAM of DSP2, and performs amplitude weighting in the internal RAM according to the signal-to-noise ratio, and then transmits it to DAC2 through PPI DMA to generate a noise waveform. If interference signals are included, DSP2 needs to read the interference data into the internal RAM through MD-MA1, and perform amplitude weighting in the internal RAM according to the interference-signal ratio, and then superimpose it with the noise, and then output it to DAC2 through PPI DMA to generate a mixed waveform of interference and noise. Among them, the PPI clock PPI_CLK signal is generated by the timer of each DSP.

The number of bits of the two DACs is 14 bits, and it is set to 4 times interpolation mode, that is, the DAC input data rate is 10MSPS and the output conversion rate is 40MSPS. The clock required for DAC conversion is shared with PPI_CLK, and the DAC is connected to the lower 14 bits PPI13~PPI0 of the BF533PPI bus. The baseband code stream is output through the PPI15 pin of DSP1, and the synchronization signal is output through the PPI14 pin of DSP1, and the output waveform is driven by 74AC11244.

The analog signal output by the DAC is buffered and amplified by AD8054, and then divided into two paths after signal and noise synthesis, which can be used as a test waveform and signal source.

If you need to simulate the communication signal environment, you need to calculate the superposition data of multiple signals in the microcomputer and then transfer it to the communication/communication signal environment data memory (SDRAM1). The other processes are the same as the communication mode. In this mode, the baseband code stream cannot be tested, but the synchronization signal can still be tested.

3 System software design

The microcomputer in the system uses Windows 2000/XP operating system, and its USB driver is developed by DDK. The control application can be developed through VS2005. The computer can generate 2ASK, 2FSK, 8FSK, 2PSK, 2DPSK, QPSK, QDPSK and other communication signals or mixed communication environment signals, narrowband Gaussian white noise and noise interference, local frequency band interference, comb interference, and related interference signals according to the user's input parameters. The data can be packaged and sent to the signal generation board through the USB interface. The computer then processes the data by sending control command words, mainly starting to output waveforms, stopping output waveforms, updating waveform data, updating communication signal environment waveform data, updating interference/noise data, and updating signal-to-noise ratio or interference-to-signal ratio.

The system software design is mainly for programming BF533. The Blackfin series DSP supports C language and assembly language in software, and supports mixed programming of the two. C language program has good structure, strong readability, and easy portability, but slow processing speed for interrupts. Assembly language has fast processing speed but poor readability and is not easy to debug. Mixed programming of C and assembly language combines their respective advantages and can construct programs with good structure and fast execution speed. The software program flow chart of this system is shown in Figure 3. In addition, the following matters should be paid attention to during programming:

(1) Whether using C or assembly language, there is only one set of identical registers available in the system. Therefore, to use these registers, the subfunction must be saved first and restored before returning.

(2) Registers must be used strictly according to their types. Registers of different types cannot be mixed.

(3) Register resources should be saved as much as possible.

(4) In order to increase the speed of code execution, it is necessary to be good at using parallel instructions.

In this system, interrupts and DMA methods are used more frequently, mainly PF interrupts, MDMA interrupts, SPI DMA interrupts and PPI DMA interrupts. The system interrupt controller can control all system interrupts and manage their priorities. DMA does not require kernel participation. During DMA operation, the kernel can be used for calculation or respond to interrupts.

After the system is powered on, DSP1 first reads its own loading code from Flash, then reads DSP2's loading code from Flash and transmits it to DSP2 through the SPI interface to load DSP2. Finally, the system clock, SDRAM, and NET2272USB control chip are initialized, and the system enters the state of waiting for microcomputer user instructions. 4

4 Conclusion

The digital communication signal generator can be realized by installing software on a general-purpose microcomputer or PC. It has low cost, high efficiency and good real-time performance. Especially in the simulation of communication countermeasure signal sources, it shows incomparable superiority.