Design of LCD driver based on MicroBlaze soft core

1 MicroBlaze Architecture

MicroBlaze uses a powerful 32-bit pipeline structure, including 32 32-bit general registers and an optional 32-bit shifter, with a clock frequency of up to 150 MHz; it runs at a speed of up to 120 DMIPS on a Virtex-4 FPGA and only occupies 950 logic cells in a Virtex-II Pro FPGA. The block diagram of the MicroBlaze soft core is shown in Figure 1. It has the following basic features:

①32 32-bit general registers and 2 special registers (program counter and status flag register).

②32-bit instruction system, supporting 3 operands and 2 addressing modes.

③ Separate 32-bit instruction and data buses, compliant with IBM's OPB bus specification (a low-speed bus connected to peripherals).

④ Directly access the on-chip block memory (BRAM) through the local memory bus (LMB, local high-speed bus).

⑤ It has high-speed instruction and data cache and three-level pipeline structure (addressing, decoding, and execution).

⑥Has hardware debugging module (MDM).

⑦With 8 input and 8 output fast link interfaces (FSL).

The interface signals in the figure are described as follows:

①DOPB, the peripheral device data interface bus inside the device, is used for data exchange between the processor and the devices on the chip.

②DLMB, local block memory bus for data exchange. This bus provides a dedicated high-speed data exchange channel between the processor core and the block memory (BRAM).

③IOPB, used to implement the bus interface of the external program memory. When the program is large, a large-capacity external memory is required. This bus provides a channel for reading instructions.

④ILMB, local memory bus for instruction fetching. This bus is connected to the block memory (BRAM) inside the device to achieve high-speed instruction fetching.

⑤MFSLO~7, master device data interface, providing point-to-point communication channel.

⑥SFSLO~7, slave device data interface, provides point-to-point communication channel.

2 MicroBlaze Embedded Development Tool EDK

Xilinx provides a complete embedded development tool EDK (Em-bedded Development Kit). EDK is a SOPC (System On Programmable Chip) system development kit launched by Xilinx in 2003. The kit integrates a wealth of development tools and a large number of IP core resources, including hardware platform generator (PlatGen), hardware simulation model generator (SimGen), hardware debugging tool (XMD), software library generator (LibGen), application software compilation tool (GNU Compilers), software debugging tool (GNU Debuggers), etc.; IP core resources include LMB and OPB bus interfaces, external memory controller (EMC), SDRAM controller, UART interface, interrupt controller, timer, etc. All these tools and resources are managed by an integrated development environment called Platform Studio XPS (Xilinx Platform Studio) in EDK. XPS provides a friendly graphical user interface (GUI) and is very easy to use. The design process is shown in Figure 2.

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3 LCD display module

The MPG240128 LCD module is a graphic dot matrix LCD that can display not only numbers, characters, but also Chinese characters and arbitrary graphics. The control chip of this module is T6963C, and the connection with the outside is only 8-bit data lines, 6 control lines and power supply. The LCD module pin description is listed in Table 1. MCtJ can realize the display control of the module by reading and writing these data lines and control lines according to the corresponding timing.

4 Interface between Microblaze and LCD module

Since the LCD module used in this article already has a display control chip T6963C, the peripheral circuit of the LCD module is relatively simple, and only the interface circuit with MicroBlaze needs to be considered. This design uses GPIO to simulate the timing of the LCD module to realize the display control of the LCD module. The interface circuit between MicroBlaze and the LCD module is shown in Figure 3.