Addressing time-to-market and design flexibility constraints using PLDs

Rapidly changing market demands drive more and more system designers to use PLDs in their embedded solutions to ease the pressure of time to market and the need for design flexibility. This market has traditionally been dominated by ASSPs and ASICs. PLDs have always been considered high-cost, high-power solutions. However, as Moore's Law continues to take effect, the unit cost of PLDs continues to decline. In high-volume applications such as communications, computing, peripherals, industry, medical, consumer and automotive, PLDs' inherent advantages of flexibility, programmability and faster time to market have become viable alternatives to ASICs and ASSPs. Moreover, silicon process and design optimizations make PLDs usable in a wide range of low-power applications.

Time to market and design flexibility

As market demands change rapidly, getting products to market quickly is more critical than ever. The most feasible solution is to shorten the development cycle to ease the pressure of time to market. Programmable logic enables designers to achieve this goal. Figure 1 compares the product development cycles of the two to illustrate how PLD products can help introduce new products.

Figure 1: Product development cycle

In addition, due to the shortening of product life cycle, the fixed function characteristics of ASSP cannot meet the needs of product changes. More and more designers use programmable logic in their products to develop new functions and standard products by modifying PLD design and reconfiguring devices to perform new operations. Using programmable logic, designers can provide several different versions when introducing products, and can update products arbitrarily in the field without additional engineering planning and reducing costs.

Production costs

Generally, a PLD is used to realize the product prototype, and then an ASIC is used for mass production. However, the ASIC development process requires a long development cycle and very high non-recurring engineering expenses (NRE). Therefore, the question becomes whether the return on investment is better with an ASIC or a PLD. Advances in process technology (90nm or more advanced) have allowed PLD manufacturers to narrow the high-volume price gap with ASICs. The unit price of ultra-low-density PLDs with 128 macro cells or less in volume is about $1.50 for 100,000 units or more.

Designing with CPLDs and FPGAs requires consideration of both static and dynamic power consumption. In most battery- powered applications, standby or quiescent current is the most critical parameter to extend battery life. In most applications, transient high currents are only short-lived (such as when talking on a cell phone). A cell phone in standby mode for most of the time consumes almost no power. Design optimizations in the system can further reduce power consumption.

Low-density, low-power CPLD

For smaller designs, such as bus interfaces, bridges, and handheld devices (see Figure 2), the use of low-power, flash-based CPLDs can provide lower-cost, low- to ultra-low-density solutions.

For power-sensitive applications, Lattice Semiconductor's ispMACH4000Z (Z stands for zero power) CPLD can provide a very good low-power solution.

Figure 2: PMP design using Lattice ispMACH4000Z

With so many devices to choose from from multiple vendors, it is important to fully understand the design requirements. The following guidelines can help designers select the appropriate CPLD:

1. What is the budget for static and dynamic power consumption?

2. What is the required I/O to logic ratio to provide bus width for bridging and interfacing applications?

3. What is the optimal density and packaging for this application?

4. What is the required voltage tolerance at the output?

5. What is the required timing margin?

6. Is the selected device field programmable and are the development tools easy to use?

7. What are the security requirements?

Different CPLD vendors have different specifications and requirements, so choosing the right device depends on which parameters are critical to the design. Table 1 shows a set of specifications provided by the device to match the design requirements.

Table 1 A set of specifications provided by this device to match the design requirements

[page]

Low power solution for medium density PLD designs

High-density designs require PLDs based on lookup tables (LUTs), such as FPGAs or crossbar PLDs. These devices can provide more embedded functions, larger memories, higher speeds, PLLs and DLLs for timing management, DSPs , and serial connections. Using a LUT structure, FPGAs can meet these design requirements and provide greater design flexibility.

Most LUT-based FPGAs do not have a "zero power" option. However, system designers can reduce power consumption by shutting down the device during certain cycles of the system. Figure 3 shows how a fast power cold start of a nonvolatile FPGA can reduce overall power consumption. Nonvolatile devices that can quickly acquire logic functions after power-up are ideal for these applications. On the other hand, SRAM-based FPGAs spend most of their cycles configuring.

Figure 3: Using a nonvolatile FPGA to reduce power consumption during operation

Most FPGAs are SRAM-based, but nonvolatile FPGAs based on flash memory are now available. Nonvolatile FPGAs offer design advantages over SRAM-based FPGAs. (See Figure 4.) In addition to the ability to manage power, the advantages of nonvolatile FPGAs include:

1. No need for a boot PROM, reducing the number of devices in the bill of materials (BOM);

2. No bit stream required, providing the highest design security;

3. Real-time in-system programmability with debugging and update capabilities;

4. Infinitely reconfigurable SRAM FPGA structure.

Figure 4: Non-volatile FPGA

The crossover programmable device MachXO from Lattice Semiconductor is a good example. Compared with traditional CPLD, MachXO devices have the advantages of both FPGA and CPLD in terms of non-volatile, low-cost, instant-on, and high-performance logic solutions.

Conclusion

With time-to-market advantages, flexibility, programmability, and low-power options, CPLDs and FPGAs have become viable design solutions for a wide range of applications in a rapidly changing market. PLDs with multiple densities and a variety of embedded features can provide fast development cycles for designs. As described in the article, they can be optimized for low power consumption and high system integration. As processes continue to improve, the price between ASICs and PLDs is rapidly approaching.