Method of Implementing FlexRay Bus on Embedded DSP

introduction

FlexRay bus is a recently launched advanced high-speed serial synchronous and asynchronous communication system that uses point-to-point (star topology) connection and unshielded or shielded twisted pair cable. FlexRay bus has fault tolerance and can provide a certain data transmission rate of 500kbps to 10 Mbps and a 24-bit CRC (cyclic redundancy) check code. FlexRay is a time-triggered bus, and all subsystems communicate continuously according to pre-set time slots. The introduction of FlexRay bus can solve the network connection problem of various electronic devices on board the vehicle, while the early CAN bus and LIN bus can no longer meet the high-speed communication requirements of modern electronic devices on board the vehicle.

This article introduces a method to implement the FlexRay bus on an embedded digital signal processor (DSP) OMAP5912. The FlexRay bus is responsible for transmitting data from various devices to the DSP, which is responsible for analyzing and processing the data. Since the system uses a DSP, it can process complex algorithms for voice and image data of vehicle electronics. This article focuses on the hardware and software connection between the DSP and the FlexRay bus.

1 FIexRay bus and its controller MFR4200

FlexRay bus is a new bus system. Its main features are:

①Supports dual communication channels, with each channel rate reaching 10 Mbps. Compared with the CAN protocol, the available bandwidth is increased by 10 to 40 times.

② The access to bus data is based on a synchronous time base. This time base is automatically established and synchronized through the protocol and provided to the application layer. The accuracy of the time base is between 0.5 μs and 10 μs. Due to the use of a synchronous time base, the message has a fixed position in the communication cycle, and the receiver already knows the time when the message arrives in advance, so it can handle various special situations accordingly according to the time.

③FlexRay bus provides two options: redundant or non-redundant message transmission. The system can be optimized to improve availability or throughput. Users can expand the entire system without adjusting the software in existing nodes. At the same time, it supports bus or star topology. FlexRay bus provides a large number of configuration parameters to support system adjustments, such as the duration of the communication cycle, message length, etc., to meet the needs of different applications.

These characteristics of the FlexRay bus make it suitable for applications such as vehicle backbone networks, distributed control systems, and safety systems. Currently, many companies have produced FlexRay bus controllers. Here, we use Freescale's MFR4200 bus controller to introduce its internal structure and the software and hardware connection method with the DSP.

The internal functional block diagram of the MFR4200 bus controller is shown in Figure 1. As can be seen from the figure, the MFR4200 bus controller is mainly composed of multiple parts such as the physical layer receive/transmit channel, the host HCSl2 interface, the MEM controller, the power management module, and the clock management module.

The physical layer channel has two independent receive/transmit channels, and the rate of each channel reaches 10 Mbps. In the working state, the host can access the receive channel FIFO and transmit message buffer of MFR4200; through the configuration, control, reading and writing of FIFO and message buffer, the physical layer data can be sent and received. The receive FIFO can store up to 59 messages, and the data frames on the bus will reach all MFR4200 on the bus. After receiving the bus data frame, each MFR4200 will pass through the receive filter; the filter will filter out the data frames that do not belong to its own address, and only store its own data frames and broadcast frames in the receive FIFO.

2 System Hardware Structure

The whole system consists of OMAP5912, MFR4200, AD/DA, human-machine interface and Flash. The hardware connection is shown in Figure 2. In the figure, DSP is the core control unit; AD is used to convert the collected analog signal into digital signal, and DA converts the digital signal into analog signal; the human-machine interface includes LCD and keyboard interface; Flash saves the program required by DSP for DSP to call when it is powered on. In addition, the HPI interface of DSP is connected to PC, so that all bus data can be stored and displayed by PC, and the data of PC can also be sent to the bus through DSP. PC or LCD and keyboard can be selected according to different needs. In the figure, EMIFS (External Memory Interface Slow) is the slow external memory interface of OMAP5912.

AD is responsible for collecting data from electronic devices, which can be temperature sensor data, color sensor data, voice signals, image signals or other signals. After processing these data, DSP sends the processed results to other nodes on the bus through MFR4200 according to different situations; on the contrary, DSP reads data frames sent by other nodes on the bus through MFR4200, processes these data frames, and sends the results to DA, which can realize the control of the status of the electronic equipment of this node.

3 Hardware Design of MFR4200 and OMAP5912

The connection between MFR4200 and OMAP5912 is the key to the system hardware connection. The specific connection is shown in Figure 3. Use the EMIFS interface of OMAP5912 to connect MFR4200. EMIFS can be easily connected to external Flash, asynchronous SRAM and other devices. The MFR4200 controller module of this system cooperates with the FlexRay bus, and its maximum data transmission rate is 10 Mbps. The EMIFS interface of OMAP5912 is suitable to meet its speed requirements.

The EMIFS of MFR4200 and OMAP5912 are connected, and MFR4200 is used as an external 16-bit asynchronous slave device of OMAP5912. Since the internal data bus width of OMAP5912 is 32 bits, and the data bus width of MFR4200 is 16 bits, each 32-bit data is divided into two 16-bit data transmissions. When MFR4200 has data to upload, the INT_CC pin is used to send an interrupt signal to the external interrupt pin EXT_INT4 of OMAP5912. OMAP5912 handles the communication with MFR4200 according to its current working conditions. OMAP5912 can also use general I/O pins to control the reset signal of MFR4200. When the response signal of MFR4200 is not received for many consecutive times, OMAP5912 can reset MFR4200 by software, thereby avoiding the interlocking phenomenon of communication. In addition, the #IF_SEL0 and #IF_SELl pins of MFR4200 are directly connected to the physical layer after being pulled up.

4 Software Design of MFR4200 and OMAP5912

The initialization process of MFR4200 is shown in Figure 4. First, set the standard voltage, which can be 5 V and 3.3 V. Since this system is connected to OMAP5912, the 3.3 V standard voltage is used. After initializing the data and address buses, read the MNR (Magic Number Register) register of MFR4200. Once the MFR4200 is initialized successfully, the content of this register is 0x0815. After that, you can set other registers of MFR4200 to read and write bus data normally.

The data communication process between OMAP5912 and MFR4200 is shown in Figure 5. After the system is initialized, OMAP5912 determines whether there is data reading or writing. Data reading is done by determining whether there is a pending hardware interrupt, which is generated by MFR4200. Once MFR4200 receives a bus data frame, it will issue the interrupt; data writing is done by determining whether the upper-layer program has data and sending a software interrupt. In the absence of data reading or writing, OMAP5912 will periodically send test commands to MFR4200 to determine whether MFR4200 is working normally. MFR4200 can also be set to a low power state as needed, so that there is no need to send test commands. If the read data has many check errors, it indicates that the current channel noise of wireless communication is very large, or the bus of MFR4200 is disturbed and disordered. OMAP5912 will reset the MFR4200 module by software, so that MFR4200 will reset the bus to avoid sending the same data repeatedly under low signal-to-noise ratio conditions and shorten invalid communication time.

Since OMAP5910 has a C55 series DSP core, some digital signal processing algorithms can be easily implemented. For voice signals, filtering can be performed to improve voice quality; for image signals, image recognition can be performed. In vehicle-mounted electronic equipment, image recognition can detect various situations in front of the car so as to perform corresponding automatic processing, making the system more practical and having a wider range of applications.

5 Conclusion

In the bus controller connection design based on OMAP5912 and MFR4200, the EMIFS interface of OMAP5912 is used to connect the bus controller MFR4200 to realize the data transmission and reception of FlexRay bus. The MFR4200 module is used to implement the bus protocol, making the system structure simple and easy to implement. Due to the use of a processor with a DSP core, the system can also easily apply various data signal processing algorithms, which is especially suitable for voice and image processing of vehicle-mounted electronic equipment.