Efinix recently announced the launch of three software-defined RISC-V-based cores, namely Ruby, Jade and Opal.
The three designs have been optimized for Efinix’s Trion family of FPGAs and offer compute and I/O capabilities from T8 to T120 devices.
The soc is pre-configured with a RISC-V core, memory, a range of I/Os, and has interfaces for embedding user functions. This allows designers to create an entire system containing embedded computing and user-defined accelerators in the same FPGA.
The Efinix RISC-V SoC comes with a complete set of tools for compiling and debugging application code on the RISC-V core, as well as example applications and tutorials. They are compatible with the entire suite of Efinix development and evaluation boards and can be instantiated using the standard Efinity tool flow.
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