Application of HPI host interface in multi-processor systems

    Abstract: HPI is a host interface configured by Texas Instruments on a new generation, high-performance DSP chip to communicate with the host. It can realize parallel and high-speed data exchange with the host computer to form a multi-machine system. The application of HPI in a certain multi-processor system is introduced, the hardware requirements of the multi-machine system and the advantages of HPI are analyzed, and the characteristics and implementation methods of HPI are introduced in detail.

    Keywords: DSP multiprocessor HPI (host interface) host communication

HPI is a host interface configured by Texas Instruments (TI) on a new generation, high-performance DSP chip to communicate with the host. It can achieve parallel, high-speed data transmission between it and the host. Currently, TI's popular DSP chips are equipped with HPI interfaces.

When a traditional microcontroller interfaces with a host computer, necessary hardware circuits need to be externally expanded. When the microcontroller needs to share RAM with the host, it is necessary to expand the RAM and trigger, latch and other chips off-chip, and then the host accesses the extended RAM through DMA, so that the host can access and share the RAM randomly or in whole blocks. In addition, at least one latch needs to be expanded off-chip so that the microcontroller can interrupt the host. TI's TMS320C5402HPI interface integrates the above functions into the DSP, making its connection with the host very simple. And because HPI is integrated into the chip, the host can achieve high access speeds, meeting the high-speed requirements of digital signal processing. This article introduces the application of the HPI interface in TI's TMS320C5402 chip in constituting a certain type of radar multi-processor system, analyzes the advantages of HPI and the hardware requirements for constituting a multi-processor system, and introduces the characteristics and implementation methods of HPI in detail.

1 HPI host interface composition

The HPI interface of the TMS320C5402 chip is divided into two types: HPI8 (8-bit host interface) and HPI16 (16-bit host interface). Their application methods are similar. Due to space limitations, this article mainly introduces HPI8. HPI8 is actually an 8-bit parallel port through which the host can directly access a section of RAM within the DSP chip. In early DSPs, this public RAM was a 2K-word dual-port RAM (for TMSVC5402, all on-chip RAMs can be accessed). When the host and DSP access the same address at the same time, the host takes priority. Since TI's DSP chips are all 16-bit, and HPI8 only has 8 data lines, data transmission must be in bytes. When the DSP and the host transmit data, HPI can automatically combine the consecutive 8-digit numbers from the external interface into 16-digit numbers and then transmit them to the host.

The HPI host consists of the following five parts:

·HPI memory (DARAM). HPI RAM is mainly used to transfer data between the DSP and the host, and can also be used as a general dual-address data RAM or program RAM.

·HPI Address Register (HPIA). It can only be accessed directly by the host pair. This register stores the address of the currently addressed HPI memory unit.

·HPI data latch (HPID). It can also only be accessed directly by the host. If a read operation is currently performed, the HPID stores the data to be read from the HPI memory; if a write operation is currently performed, the HPID stores the data to be written to the HPI memory.

·HPI control register (HPIC). Both the DSP and the host can access it directly.

·HPI control logic. Used to process the interface signals between HPI and the host.

The HPI control register (HPIC) controls the working mode of HPI. HPIC must be initialized by the host before HPI access. When the host wants to randomly access HPI RAM, it must first send an address to HPIA (HPI address register), and then access the RAM unit pointed to by the address. When the host needs to continuously access a section of HPI RAM, it needs to send the first address of the section to HPIA, and then access it by incrementing the address. At this time, the HPIA automatically points to the next unit after each host accesses a storage unit. The host can interrupt the DSP chip by setting the DSPINT bit in the HPIC. The DSP chip can also interrupt the host by setting the HINT bit in the HPIC. At this time, the HPI pin HINT is set to low level, thereby issuing an interrupt to the host. ask. The host can mask this interrupt by setting the HINT bit. The data and control pins of HPI are dedicated, which ensures the parallelism of HPI and DSP operations. The pins of HPI are in a high-impedance state when there is no host access, so they can be directly hung on the host data bus, making the hardware circuit particularly simple.

The HPI pin consists of the following parts:

(1) HD0~HD7: Bidirectional parallel three-state data bus. When no data is transmitted (HDSx or HCS=1) or EMU1/OFF=0, HD0~HD7 are all in a high impedance state.

(2) HCS: HPI chip select signal. As the enable input of HPI, it must be at low level during each addressing period, and it can also stay at low level between two addressing periods.

(3) HAS: Address strobe signal. This signal is used when the data line and address line of the host are multiplexed. This signal should be tied high when not in use.

(4) HBIL: Byte identification signal, used to identify whether the host transmits the first byte or the second byte. When HBIL=0, it is the first byte, when HBIL=1, it is the second byte.

(5) HCNTL0, HCNTL1: Host control signals, used to select the register to be addressed by the host. When HCNTL1/HENTL0 is 00, it indicates that the host accesses HPIC; when it is 01, it indicates that the host accesses the HPID pointed to by HPIA. Every time it is read, HPIA increases by 1 afterwards, and every time it is written, HPIA increases by 1 in advance; when it is 10, Indicates that the host accesses HPIA; when it is 11, it indicates that the host accesses HPID, and HPIA is not affected.

(6) HDS1, HDS2: Data strobe signals, which control the transmission of data during the host addressing HPI cycle.

(7) HINT: HPI interrupt output signal, controlled by the HINT bit in HPIC.

(8) HRDY: HPI ready. A high level indicates that HPI is ready to perform a data transfer; a low level indicates that HPI is busy completing the current transaction and is used for continuous high-speed hosts.

(9) HR/W: HPI read and write signal. A high level indicates that the host wants to read HPI, and a low level indicates that the host wants to write HPI.

(10) HPIENA: HPI enable signal. If the system selects HPI, connect it to high level, otherwise it will be left floating or connected to low level.

The host's access to a word of HPI includes two steps: first access the first byte, when HBIL is 0; then access the second byte, when HBIL is 1; these two steps form an access unit. This access unit cannot be disassembled or reversed, regardless of whether the current access is HPIA, HPIC or HPID.

HPI works in two ways:

·Shared Addressing Mode (SAM), which is a commonly used mode of operation. In SAM mode, both the host and the DSP can address the HPI register, and the addressing of the asynchronously working host can be synchronized within the HPI. If the cycles of the DSP and the host conflict, the host has priority.

· Host addressing mode (HOM) only. In HOM mode, the host can only address the HPI memory, and the DSP is in reset state or IDLE2 idle state (minimum power consumption state) where all internal and external clocks are stopped;

HPI supports high-speed transmission of data between the DSP and the host. In SAM working mode, if HPI transmits one byte every 5 clock cycles, the operating frequency of the host can reach (fdsp×n)/5. where fdsp is the clock frequency of the DSP, n is the number of cycles required for the host to perform an external addressing, usually n is 3 (or 4). Assume that the operating frequency of the DSP is 100MHz, and the clock frequency of the host can reach 60 (or 80) MHz without inserting wait cycles. In HOM mode, the host can work at a faster speed and has nothing to do with the clock frequency of the DSP.

2 Application system and results

The sliding window algorithm is a commonly used basic algorithm in digital signal processing and is widely used in communications, radar, electronic countermeasures, parameter estimation, and signal recognition. However, the sliding window algorithm is generally an ergodic algorithm, which requires a large amount of calculations and is limited in real-time processing. With the development of DSP technology and the emergence of high-speed DSP chips, the practical application of the sliding window algorithm has been expanded. This article uses two high-speed DSP chips TMS320C5402 from TI Company and uses its HPI interface to implement multiple sliding window algorithms in parallel to meet the real-time needs of a radar system for defuzzification. The system uses two TMS320C5402 chips to complete all digital signal processing algorithms. Mainly the multiple sliding window algorithm. According to the needs of the actual system, the multiple sliding window algorithm processing is distributed on two TMS320C5402, and its HPI interface is used to complete fast data exchange between multi-processors, forming a multi-machine parallel processing system to complete the multi-machine parallelization of multiple sliding window algorithms. deal with. The basic block diagram of the entire system is shown in Figure 1.

The application principle diagram of HPI in dual processors is shown in Figure 2. In this solution, connect unused signals such as HAS, HPIENA, and HDS2 to high, and leave HRDY floating. From the above analysis, the I/O ports occupied by the HPI operation control lines can be easily obtained. See Table 1 for the detailed allocation.

Table 1 I/O port allocation diagram occupied by HPI operations

interview method

    Access object

read write access

The first byte corresponds to the port address. The second byte corresponds to the port address HPIC 0h 020h HPIA 080h 0A0h HPID (address auto-increment) 040h 060h HPID (no address auto-increment) 0C0h 0E0h

When accessing the HPIC (sending a sixteen-bit data to the HPIC), first send the lower eight bits of data to the I/O space with the port address 0h, and then send the upper eight bits to the I/O space with the port address 020h. I/O space. The access methods of HPID and HPIA are the same. The following is part of the code of the HPI interface initialization program;

PORTW *AR0, 0h

LD *AR0,*-8,a

STL A,*AR0

PORTW *AR0,020h

·Code description: AR0 stores the address of the data to be sent. This program sends a 16-bit data to the HPIC.

Referring to the above steps, you can easily connect the DSP to other hosts such as FPGA, DSP, and microcontroller through HPI. Due to space limitations, only the logic signals of the FPGA when the FPGA is connected to the DSP are given here, as shown in Figure 3.

A large amount of simulation and actual measurement data show that all indicators meet the design requirements. This system has been applied in a radar system.