Audio signal acquisition and processing system based on TMS320VC5402

    Abstract: An audio signal acquisition and processing system based on TMS320VC5402 is proposed. The overall scheme and hardware and software design of the system are introduced. Discussed the design methods of analog/digital (A/D) and digital/analog (D/A) conversion circuits and how to use the multi-channel buffered synchronous serial port (McBSP) of TMS320VC5402 and the PCM1800 and PCM1744 chip interfaces to achieve audio signal collection and output. Experimental proof. The designed hardware and software system based on DSP is a good audio signal acquisition and processing system.

    Keywords: Multi-channel buffered synchronous serial port audio signal TMS320VC5402 acquisition and processing

In recent years, with the popularization of DSP technology and the emergence of low-level and high-performance DSP chips, DSP has been increasingly accepted by the majority of engineers and is increasingly used in various fields, such as: speech processing , image processing, pattern recognition and industrial control, etc., and has increasingly shown its huge advantages. DSP uses specialized or general digital signal processing chips to process signals using digital calculation methods. It has the advantages of fast processing speed, flexibility, accuracy, strong anti-interference ability, small size and high reliability. It meets the needs of fast and reliable processing of signals. Accurate, real-time processing and control requirements. Based on the TMS320C5402 chip, the author developed a real-time audio signal acquisition and processing system, which has been used as a hardware test platform for the development of sound effects.

1 System bus solution

The system bus scheme block diagram is shown in Figure 1. The audio signal (for example: the monophonic sound signal of an electric guitar is a 150mV electrical signal) is converted by a high-precision and high-speed ADC to obtain a series of digital signals, which are input into the waveform input buffer RAM in frames. Then one or several processing algorithms are manually controlled to transfer the audio signal into the interior of TMS320C5402 for high-speed operation. The processed audio signal is then input into a high-precision and high-speed DAC converter to be restored to an analog sound signal, which is amplified and output by the speaker power amplifier circuit.

The purpose of using the buffer is to perform real-time processing of sound effects. Each module in the system is processed at the same time. Some signals are being converted in the ADC, while other signals are being processed algorithmically in the DSP processor at the same time. That is, the entire system works in a pipeline manner.

2 Design of hardware circuit

A high-fidelity audio system should have a wide dynamic range, and choosing 16- to 24-bit ADCs and DACs can fully capture or restore high-fidelity audio signals. The core chip (DSP) of the system uses TMS320VC5402[1] (hereinafter referred to as 'C5402) from TI Company in the United States.

2.1 DSP chip

As a cost-effective 16-bit fixed-point DSP chip in the DSP family, 'C5402 is suitable for real-time embedded applications such as voice communications. Like other 'C54X chips, the 'C5402 offers highly flexible operability and high-speed processing capabilities. Its performance characteristics are as follows: operating rate up to 100MIPS; advanced multi-bus structure, three 16-bit data memory buses and one program memory bus; 40-bit arithmetic logic unit (ALU), including a 40-bit barrel shifter and two A 40-bit accumulator; a 17×17 multiplier and a 40-bit dedicated adder, allowing 16-bit signed/unsigned multiplication; integrated Viterbi accelerator to improve the speed of Viterbi encoding and decoding; single-cycle normalization and exponential decoding; 8 auxiliary registers and a software stack, allowing the use of the industry's most advanced fixed-point DSP C language compiler; data/program addressing space is 1M×16bit, built-in 4K×16bit ROM and 16K×16bit RAM; built-in Programmable wait state generator, phase-locked loop (PLL) clock generator, two multi-channel buffered serial ports, an 8-bit parallel HPI port to communicate with an external processor, two 16-bit timers, and 6-channel DMA controller Low power consumption. Compared with other chips in the 'C54X series, '5402 has the characteristics of high performance, low power consumption and low price. It uses a 6-stage pipeline, and when RPT (repeated instructions), some multi-cycle instructions become single-cycle instructions; the chip's internal RAM and ROM can be flexibly set according to the OVLY and DROM bits in the PMST register. These are beneficial to the optimization of the algorithm.

'C5402 is powered by 3.3V and 1.8V power supplies, of which the I/O is powered by a 3.3V power supply, and the core of the chip is powered by a 1.8V power supply. In fact, only 5V power supply is commonly used, so a power conversion chip must be used. Select two power conversion chips, TPS7301 and TPS7333 (both are power conversion chips designed by TI to cooperate with DSP), and connect appropriate peripheral resistors respectively to form a resistor divider, and you can adjust the output voltages of the two chips respectively. for 3.3V and 1.8V.

PCM1800 is a dual-channel monolithic Δ- Σ type 20-bit ADC, powered by a single +5V power supply, with a signal-to-noise ratio of 95dB and a dynamic range of 95dB. It has a high-pass filter embedded inside and has a PCM audio interface and four data formats. It is divided into two modes: master control and controlled mode, and the sampling frequency can be selected as 32kHz, 44.4kHz and 48kHz.

When PCM1800 forms an audio signal acquisition system, it mainly involves the timing pairs of BCK (bit clock signal), LRCK (sampling clock signal), FSYNC (frame synchronization signal), DOUT (digital signal output), and SYSCLK (system clock input). There are pins required. By programming the pins MODE0 and MODE1, the PCM1800 can work in the master mode (Master Mode). At this time, BCK, LRCK, and FSYNC are all used as outputs, and their timing is controlled by the clock generation circuit inside PCM1800. But SYSCLK can only be provided externally (here it is provided by the TOUT pin output signal of 'C5402). The system clock of PCM1800 can only be 256fs, 384fs or 512fs, where fs is the single-frequency signal sampling frequency. In master control mode, FSYNC is used to indicate the valid data output by PCM1800's DOUT. Its rising edge indicates the start of a frame of data, and its falling edge indicates the end of a frame of data. The frequency of FSYNC is 2 times the sampling clock frequency LRCK. In this mode, the frequency of the bit clock signal BCK is 64 times the sampling clock frequency LRCK.

By programming the FMT0 and FMT1 pins of PCM1800 (FMT0=1, FMT1=0), the data format output by PCM1800 can be set to the 20-bit IIS format. In order to ensure that data processing does not affect the reception of new data and the ongoing data processing process when receiving data, a multi-channel buffered synchronous serial port (McBSP) is used. After PCM1800 is connected to 'C5402, 'C5402 uses buffered serial port 0 to receive data. Various synchronization signals are generated by PCM1800. 'C5402 passively receives various information. The hardware wiring diagram of PCM1800 and 'C5402 is shown in Figure 2.

2.3 D/A circuit

PCM1744 is a two-channel stereo DAC that contains digital filters and output amplifiers with a dynamic range of 95dB and a variety of sampling frequencies available, up to 96kHz. Use 24-bit IIS data input format. The operation of PCM1744 mainly involves LRCIN (sampling clock signal input), BCKIN (bit clock signal input), SCKI (system clock input), and DIN (data input), which have timing requirements. After PCM1744 is connected to 'C5402, '5402 uses buffered serial port 1 to send data. Various clock signals are generated by 'C5402, and PCM1744 passively receives various information. The system clock signal (SCKI) of PCM1744 is provided by the TOUT pin of 'C5402. TOUT is the timer output signal pin of 'C5402. It has strong driving capability and can drive multiple chips. The data receiving clock format of PCM1744 must be IIS format. When C5402 sets various clock modes in the buffer serial port register, it must meet the requirements of IIS format. 'C5402, as an active working device, can adjust its buffered serial port output signal. The output sampling clock signal and bit clock signal can be set in the McBSP registers SRGR1 and SRGR2. The setting follows the principle of Figure 3.

After PCM1800 completes the audio signal collection, the corresponding processing algorithm is embedded in the external expansion program memory of the DSP. After the voice signal is processed, it is output from PCM1744.

3 Software design

The software part mainly includes DSP programming and PC programming. The main tasks of the DSP process are to initialize, manage the resources on the board and complete the audio processing algorithm. Please refer to the relevant information. PC programming focuses on managing DSP operations and writing application layer software.

3.1 A/D and D/A programming

In order to obtain excellent audio output in the 20kHz audio frequency band, the sampling frequency of A/D and D/A should reach 44.1kHz or 48kHz. To correctly write a program for sampling and outputting audio signals, the McBSP related registers of the 'C5402 (spcr1, spcr2, rcr1, rcr2, xcr1, xcr2, srgr1, srgr2, mcr1, mcr2, rcera1, rcerb1, xcera, xcerb, pcr1) Make the correct settings [1] to meet the various timing requirements (bit synchronization, frame synchronization, clock signal, etc.) of 'C5402 and PCM1744, PCM1800. In order to enable TOUT to provide clock signals to peripheral devices, the timing and interrupt operations of the DSP are designed. For details, please refer to the Spru302.pdf information provided by TI.

3.2 Programming of DSP and PC

The DSP program first initializes the 'C5402 and analog interface. After allocating the corresponding buffer and generating the corresponding interrupt, various sound effect processing algorithms are performed, such as: compression, distortion, frog sound, room noise suppression ZNR, amplification, equalization, chorus, flanging, delayed reverse singing, etc. Or a mixture of several algorithms.

PC programming includes DSP interface part and application layer programming part. At the beginning of the PC program, the program that interfaces with the DSP first calls the initialization function to download the DSP program to the DSP (the initialization program loads a small bootloader into the DSP, and then loads the entire program piece by piece through the bootloader loaded into DSP). After the initialization is completed, the program that interfaces with the DSP reads the DSP processing result frame or the DSP request frame at the designated location according to the customized "communication protocol" and hands it to the upper layer (application program) for processing. The application program also issues various commands to the DSP through some programs that interface with the DSP. The upper-layer application is the interface for users to use the system, which provides functions such as voice database management and system management.

3.3 Program optimization based on optimization tools

According to the user's requirements, select the C program optimizer and assembly optimizer to optimize the specific performance of the encoder such as code length, calculation speed, etc. The method of use is to set different compilation options during compilation (Built Options) to control the optimization goals. Based on our practice, we believe that choosing the following items for optimization will have a greater impact on improving calculation speed:

(1) -pm: Program-level global optimization, including external access of the program, optimization of global variables and external calls of functions.

(2)-o3: Using three-level optimization technology. The first-level optimization mainly completes the elimination of useless assignments and local public expressions, etc. The second-level optimization mainly completes the optimization of loop algorithms and converts array access in the loop into pointer increment form and implements loop expansion. Eliminate global public expressions and useless assignments, etc. The third level of optimization mainly completes the elimination of redundant code, simplifying expressions and statements, using inline (inline) functions and expanding them, etc. -03 On the basis of the above, it also completed the elimination of never-used functions, reordering function declarations and inlining the use of functions.

(3) Use inline functions (intrinsic). 'The intrinsi provided by the C5402 compiler can quickly optimize C code. Intrinsic is a special function (ETSI function) that maps directly to an inlined 'C5402 instruction. Intrinsic is represented by a leading underscore and is used in the same way as a function call.

Actual results show that if you select the above items for optimization, as long as the compilation options are appropriately selected, the effect is very significant, and the calculation speed can be increased by 5 to 10 times. Of course, the code length will increase slightly.

3.4 Introduction to audio signal processing algorithms[2]

In the process of picking up and transmitting sound, due to the limitations of equipment and devices, its amplitude response to frequency is not consistent, and it is very likely that the gain of some frequency components will be too large or too small. For such defects in frequency response characteristics, appropriate adjustments are required. An equalization algorithm for audio signals, which adjusts the gain of certain frequency components through software design to enhance or attenuate them. After the sound signal is equalized, it can make up for the lack of frequency response characteristics, and can also artificially create some better sound effects.

Of course, audio signal processing is a very complex process. For example, electric guitar sound effects also include algorithm processing such as modulation and delay reverb.

The audio signal acquisition and processing system designed in this article has been used as a hardware test platform for the development of electric guitar and other sound effects devices, and has the following algorithms: compression module, distortion module, ZNR/AMP module, equalization module, modulation module, and delay reverb module . Each module can be used individually or in series, and uses two LED digital displays to indicate the selected mixed sound mode. It greatly changes the timbre of the electric guitar itself, and can produce a variety of individual timbre effects such as compression, distortion, frog sound, room noise modulation (ZNR), amplification, equalization, chorus, flange, delay response, etc., or simultaneously Use several timbre effects to greatly enrich the live performance of electric guitar. Input the same electric guitar signal into ZOOM 505 (produced by Japan ZOOM Company) and the system respectively, and then analyze and compare the output waveforms in the time domain and frequency domain as well as amplitude and phase, and optimize the algorithm. It can be found that the final The sound effects are almost the same. In addition, in this system, there are both A/D and D/A, forming a closed loop that can be self-recovery; while the algorithm is concentrated in the DSP chip for modular processing, which brings convenience to the design and debugging of the system. Great convenience. Therefore, if we can design an electric guitar sound effector with functions and effects comparable to ZOOM 505 based on the audio signal acquisition and processing system with TMS320VC5402 DSP chip as the core device proposed in this article, it can fundamentally change the current domestic The electric guitar sound effector market is basically monopolized by foreign products [3], which has strong practical value.