Design of TMS320C30 and A/D and D/A interfaces

    Abstract: A design method for the interface between DSP and A/D and D/A with minimal hardware generation and simple software control. This method uses the program control capability of DSP to coordinate the work of various modules such as A/D and D/A, and does not require bus isolation. This method has been successfully applied to the acquisition and processing system of automobile anti-collision radar signals.

    Keywords: DSP A/DD/A timing relationship

MAX153 and MX7545 are 8-bit A/D converters and 12-bit D/A converters launched by the American MAXIM company in recent years. The MAX153 has a sampling rate of up to 1MSPS, and the MX7545 has a digital-to-analog conversion speed of 4MSPS. They integrate tracking/holding devices, so the data acquisition and filter generation circuit structures composed of them are relatively simple. Compared with other similar products, they have the advantage of high performance/price ratio, so they can be used as data acquisition and waveform generation devices or in systems with high dynamic performance requirements such as high-speed data acquisition, digital signal processing and variable gain amplifiers. The control signal generating device is ideal. The MAX153 and MX7545 can easily interface with general microprocessors without having to worry too much about timing issues. However, when they interface with a high-speed digital signal processor (DSP) at the same time, timing issues and other issues need to be carefully considered in the design of software and hardware. Let's first briefly introduce the working modes of MAX153 and MX7545, and then take their interface with TMS320C30 digital signal processor as an example to introduce the software and hardware design method of the interface in detail.

1 Working mode of MAX153

Depending on the signal on the MODE pin, MAX153 has two different operating modes. When MODE is connected to ground (0V), the converter is in RD operating mode; when MODE is connected to high level (+5V), the converter is in WR-RD operating mode. Due to space limitations, only the WR-RD working mode will be introduced below.

As can be seen from Figure 1, the converter starts on the falling edge of WR. When WR goes high, the high 4-bit data has been converted and sent to the output buffer. At the same time, the low 4-bit data starts to be converted. INT after 380ns goes low, indicating that the lower four bits of data conversion have also been completed. There are two ways to read data. Here we only introduce the data reading method in the fastest working mode.

Figure 1 shows the conversion timing diagram controlled by external signals. In this mode of reading data, the RD signal is effective in advance and the fastest conversion time can be obtained. Generally, RD turns low 250ns after the rising edge of WR, and the conversion can be completed to obtain the data. INT goes low on the falling edge of RD and then goes high on the rising edge of RD or CS.

2 Working modes of MX7545

Like general D/A converters, the MX7545 also has two operating modes: current and voltage. Among them, the current working mode is divided into two types: unipolar and bipolar. Only the unipolar current working mode is introduced here. Whether it is current working mode or voltage working mode, the working sequence of MX7545 is the same, as shown in Figure 2. Among them, within a conversion cycle of MX7545, the effective time tcs of the chip select signal CS requires 180ns, and the effective time tWR of the write signal WR requires 160ns.

3 Hardware interface

According to the requirements of the automobile anti-collision radar system, the echo signal of the radar needs to be collected while sending the triangular wave FM signal. Due to system resource limitations, we configure A/D and D/A on the expansion bus of TMS320C30 at the same time. TMS320C30 is TI's general-purpose DSP chip. It has strong floating-point/fixed-point data computing capabilities and high processing speed. It is especially suitable for real-time data acquisition and computing processing (such as FFT, FIR, IIR filtering, etc.). Figure 3 is the hardware connection diagram of this interface. In the figure, XA[8~10] are three of the address lines of the expansion bus. After decoding by the decoder (74LS138), its outputs Y1 and Y2 are connected to the chip select signal (CS) terminals of MX7545 and MAX153 respectively. , as their chip select signals respectively. RD/WR is the read and write control signal of the TMS320C30 expansion bus, IOSTRB is the strobe pulse of the expansion bus, and XD[0~11] is the data bus of the expansion bus. The read and write signals of A/D and D/A are determined by the read and write signals and strobe signals of the DSP expansion bus. Their relationship can be expressed by the following formula:

/WR=RD/WR+IOSTRB

/RD=RD/WR+IOSTRB

When the A/D is working, Y2 addressing selects MAX153. When the DSP write signal is valid, the A/D conversion starts; when the DSP read signal is valid, the A/D outputs data. When D/A is working, Y1 addressing enables the MX7545. When the write signal of the DSP is valid, the D/A conversion starts. MAX153 works in the fastest conversion mode, and the port address is 804100; MAX7545 works in the universal unipolar current operating mode, and the port address is 804100. As can be seen from the figure, its hardware circuit is relatively simple.

4 Timing coordination and program preparation

The following will introduce the timing coordination issues between the D/A's universal current operating mode and the A/D's fastest operating mode with the TMS320C30 DSP interface.

4.1 Timing coordination issues

From the connection method and working sequence of the system hardware circuit, the timing relationship between "start conversion" and "read data" can be analyzed. A dummy write operation can make A/D's /WR valid and start conversion. As far as the port gated by the signal line IOSTB of the DSP expansion bus is concerned, two clock cycles are required for reading and writing. When the DSP uses a 33.3MHz clock, each clock cycle H1 is 60ns (ie, divided by two of the main clock). As can be seen from Figure 1, the minimum start-up conversion time tWR requires 250ns, so a bus waiting period needs to be inserted. If 4 waiting cycles are inserted, tWR is 60×5=300ns at this time. Excluding the transmission delay of the high-speed decoder of 17ns, the actual pulse width of WR is much larger than the minimum pulse width of tWR specified by MAX153 of 250ns, so the A/D is started. The conversion is reliable.

As can be seen from Figure 1, the conversion time tRD required by MAX153 must be greater than 250ns, so a delay time of 300ns needs to be added here. At this time, reading the A/D converted data is also reliable. Then read and convert the A/D data, and then send the data to D/A. As can be seen from Figure 2, tCS requires at least 180ns, and tWR requires at least 160ns, so setting 4 bus waiting periods can fully meet the requirements.

4.2 Writing assembly programs

Since this circuit is used in the automobile anti-collision radar signal acquisition and processing system, the function that this circuit should complete is to collect the echo signal of the radar while sending the triangular wave required by the radar, that is, both must be completed at the same time. The specific procedures are as follows:

SECT "INIT"

.TEXT

BR INIT

INIT LDP 0, DP; set page pointer

LDI 1800H, ST; disable global interrupt

LDI @STCK, SP; Set the system stack pointer

LDI @CTRL, AR0; set the first address of the register

LDI @PRIMARY, R0; the memory on the main bus is in 0 wait state

STI R0,*+AR0 (100)

LDI @SECONDARY, R0; expansion bus waits for 4 bus cycles

STI R0,*+AR0(96)

LDI @DADAT,AR0; Set the address where D/A data is stored

LDI 0H, R0

LDI @STEP, R1; set the increasing step size

LDI @LEH1, RC; Set the number of points on the rising edge of the triangle wave

RPTB LODUP; Load the D/A rising edge data to be sent

STI R0,*AR++(1)

LODUP ADDI R1, R0

NOP

LDI @LEH1, RC; Set the number of points on the falling edge of the triangle wave

RPTB LODOW; Load the D/A falling edge data to be sent

STI R0,*AR++(1)

LODOW SUBI R1, R0

LDI @DAPORT, AR0; Set D/A port address

LDI @ADPORT, AR1; Set A/D port address

LDI @ADDAT, AR4; fake read once, reset A/D

LDI 0, R4

LDI @DADAT, AR3; assign D/A data address

LDI @LEH, RC; set the number of cycles

RPTB LOOP; block loop

STI R4, *AR1; write once and start A/D conversion

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

LDI *AR1, R3; read A/D data

STI R3, *AR4++(1); store A/D data

LDI *AR3++ (1), R0; transfer D/A data

LOOP STI R0, *AR0; send data to D/A

BR PROSESS; transfer to subsequent signal handler

.DATA

CTRL .WORD 808000H; Control register first address

PRIMARY .WORD 00000808H; Main bus control word

SECONDARY .WORD 00000088H; extended bus control word

STCK .WORD 0809F00H; system stack pointer value

DAPORT .WORD 804100H; D/A port address

ADPORT .WORO 804200H; A/D port address

DADAT .WORD 10000H; the first address to store D/A data

ADDAT .WORD 11000H; the first address where A/D data is stored

LEH .WORD 0682H; Block cycle length control word

STEP .WORD 02H; step size control word

.END

According to the program, the timing of the system can be obtained, as shown in Figure 4.

Based on the above hardware and software design, the following can be obtained from the timing diagram:

AD startup conversion time: 60×5=300ns

Waiting time for A/D conversion: 60×5=300ns

Reading A/D data time: 60×5=300ns

Time to store A/D data and transfer D/A data: 60×7=420ns

Time to send D/A data: 60×5=300ns

The time required from sending D/A data to starting the next A/D conversion: 60ns

So, the total conversion time is:

Ts=300+300+300+420+300+60=1680ns

Therefore, its conversion frequency is:

Fs=1/Ts=1/1.68 μs=595.2kHz

Issues that need attention in program design include:

(1) Before starting the A/D conversion, a false read should be performed to reset the A/D to avoid unreliable operation.

(2) The expansion bus of TMS320C30 should be set with 4 waiting cycles to ensure that A/D and D/A cooperate with the DSP to send and receive data timing.

(3) The design of the interface circuit between A/D or D/A and DSP or MCU. The most important thing is to ensure that their timing is correct. Especially when they are connected to the DSP at the same time, their timing cooperation issues should be carefully considered from the software side.

MAX153 and MX7545 not only have strong functions, but also can easily interface with general microprocessors. However, there are some special issues to consider when interfacing with DSP. In view of the fact that there are few articles detailing the convenience of DSP interface with A/D and D/A converters at the same time, we choose one of the interface methods to introduce it. For the application of other modes, you can also refer to the method introduced in this article. We have successfully applied this design to its DSP automotive anti-collision radar signal processing system.