Dual CPU digital signal processor with ARM core

    Abstract: This article mainly introduces the structure, function and characteristics of TMS320VC5470, the latest fixed-point digital signal processor launched by American TI Company. The TMS320C54x digital signal processor and ARM7TDMI RISC MCU integrated into the device and their connections are introduced respectively. It has certain reference value for choosing TMS320VC5470 as a digital signal processor to build embedded systems.

    Keywords: TMS320VC5470 DSP MCU TMS320C54x ARM7TDMI

introduction

TMS320VC5470 (5470 for short) is a CPU fixed-point digital signal processor that integrates a DSP subsystem based on the TMS320C54x architecture and a RISC microcontroller subsystem based on the ARM7TDMI core. Compared with previous devices, it has increased speed, reduced power consumption, and greatly improved programming flexibility, which is conducive to product software and hardware upgrades and is used to implement products with special functions. By rationally arranging software and hardware resources, you can also save investment and speed up time to market.

1 TMS320VC5470 features and functional block diagram

*A dual-CPU processor that integrates a TMS320C54x architecture DSP and an ARM7TDMI RISC MCU;

*16-bit low-power DSP with 72K×16-bit integrated SRAM, speed up to 100MHz;

*Advanced power management and low-power modes for DSP and MCU subsystems;

*Integrated DSP subsystem peripherals, including 2 high-speed full-duplex multi-channel buffered serial port McBSPs, allowing the DSP core to directly interface with the codec (CODEC); DMA controller with 6 independent channels; ARM side interface ( port interface) provides a 2K×16-bit shared memory interface for effective information exchange between the CPU of the MCU subsystem and the DSP subsystem; the external memory interface EMIF (External Memory Interface); can extend the external bus cycle to 14 Software programmable wait state generator for machine cycles; 1 software programmable hardware timer for control functions; programmable phase locked loop PLL clock generator.

* ARM7TDMI RISC microcontroller core with 16K bytes of integrated SRAM and enhanced simulation performance, allowing the operating speed to be as high as 47.5MHz;

*Integrated MCU subsystem peripherals, including universal asynchronous receiver transmitter UART, UART/IrDA interface supporting SIR protocol, serial peripheral connection SPI, 36 general-purpose I/O pins, I2C interface, 2 general-purpose timers, 1 Watchdog timer, interrupt handler, external storage interface supporting Flash/SRAM/SDRAM/ROM, flexible clock management for MCU peripherals, and programmable phase-locked loop clock generator.

*Simulation logic based on on-chip scanning, IEEE Standard 1149.1+ (JTAG) boundary scan logic for DSP and MCU cores;

*Supports scan-based simulation of DSP and MCU cores.

Figure 1 is the functional block diagram of the TMS320VC5470 device. This device consists of 2 subsystems: DSP and MCU.

2 Introduction to DSP subsystem functions

The DSP subsystem is based on the TMS320C54x, on-chip memory and peripherals, and is code compatible with other C54x products. The DSP subsystem includes a DSP CPU core, a phase-locked loop for clock generation, an interface to connect to external parallel devices, a timer, 72K words of RAM, 2 multi-channel buffered serial ports, and 1 port that allows the MCU to access the DSP subsystem Some memory-mapped interfaces and a JTAG interface.

(1) DSP core

The fixed-point digital signal processor (DSP) of the DSP subsystem in the 5470 device uses an advanced improved Harvard architecture, which has 1 program memory bus and 3 data memory buses. This processor provides a highly parallel arithmetic logic unit (ALU), dedicated hardware logic, on-chip memory, and additional on-chip peripherals. The foundation for the speed and flexibility of DSP operations is its highly specialized instruction set.

The separation of program and data space and 4 parallel buses allow simultaneous access to the program's instructions and data. Each bus accesses different memory spaces to implement different DSP operations, thus providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Parallel-stored instructions and application-specific instructions can fully exploit this structure. Additionally, data can be transferred between data and program space. This parallelism ensures that a powerful set of operation instructions including arithmetic, logic and bit operations can be completed within 1 machine cycle. The DSP subsystem also contains a simulation port dedicated to in-circuit simulation. This port is directly accessed and provided by TI's Extended Development System (XDS) hardware emulator. In addition, the 5470's DSP subsystem also includes control mechanisms to manage repeated operations, function calls, and DSP interrupts.

(2) DSP memory

The 5470 device provides 72K words of on-chip RAM as follows: 40K words of program space single-side access RAM (SARAM), 16K words of data space dual-side access RAM (DARAM) and 16K words of data space single-side access RAM (SARAM). Each DARAM block can perform 2 DSP accesses in 1 machine cycle. The DSP subsystem can also perform multiple accesses to separate memory blocks within 1 machine cycle. After a normal reset, the data space RAM block between addresses 0x0000~0x7FFF is only mapped as data storage space, and the program space RAM block between addresses 0x06000~0x0FFFF is only mapped as program space. DSP memory mapping has 2 modes: normal mode and API startup mode. Reset, interrupt and trap vectors are located in program space. When a trap occurs, the processor loads the trap address into the program counter (PC) and begins executing code from this vector location. After the device is reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the start address of any 128-word page in program space by loading the interrupt vector pointer (IPTR).

(3)DSP register

The 5470 device has 27 register-mapped CPU registers (MMR), which are mapped to the data memory space at addresses between 0H and 1FH. The device also has a peripheral-related memory-mapped register set.

The bank-switching control register BCSR (Bank-Switching Control Register) of the 5470 device not only controls the occurrence of the bank-switching wait state similar to the 5409, but also controls some characteristics of the 5470. The split switching wait state refers to the automatic insertion of 1 cycle when the DSP subsystem cross-accesses the memory split boundary in the program or data memory space. When the boundary between data space and program space is accessed across, a split switching wait state will also be automatically inserted. The features of the 5470 controlled by BSCR include control of the functional configuration of some external memory interfaces of the DSP subsystem, as well as some content about the interface that the MCU can use to access a certain RAM part of the DSP subsystem. The BSCR register also provides the DSP with some control over the ARM programming interface. This mechanism allows the MCU to access the internal RAM portion of the digital signal processor. In addition, it also includes control of API mode (APIMODE bit), 1 MCU interrupt (HINT bit), and DSP memory map selection (ABMDIS bit). Figure 2 shows the bit structure of the BSCR register, and Table 1 lists the functions of each field.

Table 1 Functions of the bit fields of the split switching control register

(4) DSP peripherals

DSP子系统提供了与5409类似的高速全双工串口——2个多通道缓冲串口（McBSPs）。它们允许与其它的54x设备、编解码器及系统中的其它设备进行直接接口。

DSP子系统包括1个6通道的DMA控制器，用于执行独立的数据传输。在DMA控制器进行DMA传输时有几点限制；第1，DMA控制器能访问通常在程序空间的RAM，不能访问在MCU子系统中执行的RAM，不能访问在DSP数据空间与API接口连接的RAM；第2，DMA控制器不能在McBSP DRR和DXR寄存器之间进行数据传输，不能在McBSP DRR或DXR寄存器与外部资源之间进行数据传输；第3，DMA控制器不能对外部资源进行32位的访问。

MCU和DSP之间通过片上共享的API存储器进行信息交换。API存储器是一个8K×16位字的DARAM（Dual-Access RAM）块。API存储器还可以被DSP用作通用数据或程序DARAM。在这个电路中，只有DSP存储器有DARAM。API通过分体切换控制寄存器可以选择两种操作模式之一：共享访问模式SAM（Shared-Access Mode）和主机模式HOM（Host-Only Mode）。在SAM模式下，DSP和MCU都可以访问API存储器。来自MCU的异步主机访问在内部被重新同步。如果DSP和MCU试图在同一时间进行访问操作，那么MCU进行优先访问，而DSP则等待1个周期。当DSP处于IDLE1模式时，SAM可以运行。在HOM模式下，只有MCU可以访问API存储器，对于DSP则禁止读访问。当DSP从一个复位相退出时，缺省配置是SAM模式。当DSP处于正常操作模式或IDLE1模式时，通常选择SAM模式；当DSP处于IDLE2或IDLE3模式时，通常选择HOM模式。

（5）DSP电源管理

DSP子系统具有3种省电模式，分别由IDLE1、IDLE2和IDLE3指令激活。在这种3种模式下，C54x DSP核进入睡眠状态，从而与正常模式相比大大降低了功耗。这3种模式的区别于对芯片内部模块的关闭程序及唤醒方式不同。在IDLE1模式下，关闭除DSP系统时钟以外的所DSP活动。因为系统时钟要用于DSP子系统外围模式，所以DSP外围电路能够继续工作。这样，外围（例如串口和定时器）则可以命名DSP离开省电状态。在IDLE2模式下，同时关闭DSP子系统的外围及DSP核，但是DSP子系统的锁相环（PLL）时钟放大器则仍将保持活动状态以便可以从IDLE2状态快速恢复。由于DSP子系统的外围在这种模式下被关闭，它们不能像IDLE1那样通过产生中断来唤醒C54x。然而，由于外围的完全关闭使功耗大大地降低了。为了终止IDLE2，可以通过复位或激活中断0来实现。IDLE3模式与IDLE2模式类似，只不过它还将关闭锁相环（PLL）电路。IDLE3用于获得最小可能的DSP功耗。另外，如果系统要求C54x运行在较低的速度下以节省功耗，那么IDLE3状态允许外部重新配置DSP PLL。与IDLE3一样，通过复位或激活断0可以终止IDLE3。

3 MCU子系统功能介绍

5470 MCU子系统包括TI公司的增加了仿真特性的ARM7TDMI微处理器核以及一些外围，包括SPI和I2C接口、通用异步收发器、定时器、通用输入/输出接口和外部存储器接口。MCU子系统提供4K×32位的通用RAM和4K×32位的太网包RAM。

（1）MCU核

MCU子系统使用TI公司的增加了仿真特性的ARM7TDMIE核，它是ARM公司ARM7TDMI核的一种衍生品。ARM7TDMI处理器核是ARM7 Thumb家庭中的一种，是一种低功耗3的32位RISC处理器，并且组合了Thumb 16位的压缩指令集。这种微处理器可以通过执行中2位或16位指令来处理32位、16位或8位数据。由于引入Thumb而获得的卓越的代码密度，可以降低对存储器大小的需求，并且可以从16位宽的存储器获得32位的系统性能，从而降低了系统的成本。

MCU存储器空间包括内部RAM、内部外围、用于访问外存储器和外区域以及外部SDRAM。

（2）MCU存储器接口

MCU存储器接口通过1条32位宽的数据总线使MCU与内部及外部的存储器和外部设备连接。这条总线支持MCU访问8位、16位和32位的数据。所有的外围控制寄存器均为32位，因此只能使用32位的操作进行访问。

MCU存储器接口允许端配置，以便保证所有的外部设备工作在同样的端模式下。MCU存储器接口还提供对外部访问的管理，所支持的外部设备包括ROM（Flash）、SRAM和SDRAM。外部数据部线是一种32位的双向总线。MCU对内部外围和内部存储器的访问通常在0等待状态执行。SDRAM刷新周期使任何MCU访问发生延迟。MCU对外部SDRAM存储器访问的定时由SDRAM接口寄存器控制。

API接口用于MCU对DSP存储器中的某一小部分进行访问，它提供了一条通向DSP子系统中的API RAM的16位数据通路。所有的32位事务被分成2个16位的API事务。API接口支持向连续的访问操作之间可编程地插入等待状态，以保证MCU子系统和DSP子系统之间的信号同步。

（3）MCU外围

5470MCU子系统的外围主要包括通用异步收发器（UART）接口、串行外围接口（SPI）、通用I/O口、I2C接口、定时器和中断控制器。

The UART module performs serial-to-parallel conversion on character data received by the processor through two 64-bit deep first-in-first-out stacks, and performs parallel-to-serial conversion on character data transmitted by the processor. SPI is a bidirectional 3-way interface used to provide a 3-way serial interface for data transfer from or to external devices. This serial port is completely controlled by the MCU memory interface. It is based on a circular shift register and allows 2 transmission modes, namely parallel input, serial output and serial input, parallel output. 54703 provides 36 general-purpose I/O ports (GPIO), which can be configured in read or write mode through internal registers. These GPIOs are divided into 2 groups: GPIO (19:0) and KBGPIO (15:0). KBGPIO are keyboard GPIO pins, some of them have internal pull-up resistors, but they operate similarly to GPIO (19:0) pins. The main I2C interface module provides an interface between the MCU subsystem bus and I2C pins, which allows the MCU to control external devices connected to the I2C pins. The I2C interface is actually a parallel-to-serial and serial-to-parallel converter. The parallel data received from the MCU must be converted into an appropriate serial format on the I2C bus and transmitted to the external device. The serial data received from the I2C bus must be converted into an appropriate parallel format and transmitted to the MCU. The 5470 MCU subsystem includes three 16-bit timers, which can be configured in two modes: "autoload" or "countdown to 0 and stop". When the timer counts to 0, an interrupt is generated to the MCU. Timer 0 can be configured as a watchdog timer or a general-purpose timer, and Timer 1 and Timer 2 are general-purpose timers. The watchdog timer resets the MCU subsystem when the countdown reaches 0 to prevent the user program from being blocked by an infinite loop and causing the program to lose control. The interrupt controller of the MCU subsystem performs priority and shielding control on the 16 interrupt sources (IRQ0~15) of the MCU subsystem. It can also divide these interrupts into 2 interrupt inputs of the MCU: nIRQ (low priority interrupt request) and nFIQ (fast interrupt request). It can receive interrupts both from the internal module and from the external chip environment. External interrupts can be provided through GPIO and/or KBGPIO pins.

(4) MCU power saving mode

The MCU and its subsystem peripherals can be shut down and woken up by setting the appropriate bits in the CLKM_BER and WAKEUP_REG registers. It is the software's responsibility to set ARM_CLOCK to bypass or low-frequency mode between MCU shutdowns. The MCU is woken up by the first interrupt from a peripheral.

(5) MCU external clock management

The 5470 device is clocked by the peripheral clock input signal REFCLK. The 5470 REFCLK input does not provide a clock oscillator. So it must be driven by a square wave input signal encountering VIH and VIL requests. The clocks for both the DSP and MCU subsystems are derived from REFCLK using phase-locked loops. After reset or power-up, the contents of the respective CLKMD registers in the two subsystems are determined by the status of the programmable internal ports on the respective phase-locked loops. For the MCU subsystem, these internal ports are hardwired, so programmable capabilities in default mode are not available. For the DSP subsystem, the programmable internal port of the DSP PLL is connected to the output of the register DSP_REG, which is controlled by the RISC processor. In this way, under the control of the MCU subsystem, the default value of the DSP PLL is allowed to be programmable. Figure 3 is a block diagram of the clock management module.

(6) Initialization

RESET is the master reset input that resets the DSP and MCU subsystems. The RESET_OUT signal can be used to reset external devices under the control of the MCU. When the MCU subsystem is reset, the MCU program counter starts execution from address 0x00000000; when the DSP subsystem is reset, the DSP program counter starts execution from address 0xFF80. Each MCU subsystem peripheral can be independently reset through the control bit of the MCU subsystem register RESET_REG. By default, these bits are set as soon as an MCU subsystem reset is activated, causing all MCU subsystem peripherals to be active.

The 5470 provides flexible simulation performance. It supports both TI's simulation tools and tools developed by third-party companies. Since these simulation tools may recognize both the C54x DSP core and the ARM7TDMIE core, or may only recognize the C54x DSP core, or only the ARM7TDMIE core, or only the ARM7TDMI core, multiple simulation modes are required. To allow configuration of the internal JTAG chain used by various emulators, the 5470 samples the EMU1 and EMU0 pins on the rising edge of TRST. Depending on the values ​​of these pins, the internal scan chain is configured into different emulation modes.

Conclusion

Since digital signal processors entered the market in the 1980s, they have been rapidly and widely developed in various fields of society. Digital signal processors are used in fields ranging from communications, networks, and radar to motor control, digital cameras, and hearing aids. Since TI's latest dual-core fixed-point digital signal processor TMS320VC5470 has the characteristics of dual CPUs, low power consumption, and fast speed, it provides a more advanced optional device in the field of digital signal processing. We hope that the introduction in this article can help hardware or software engineers choose this device for application development.