Radar digital pulse width identification circuit implemented with programmable devices

    Abstract: In view of the situation that there is still a lot of noise interference after digital quantization of radar video signals, the basic characteristics of the noise level are analyzed, and the principle circuit of using the programmable device ispLSI1016E to realize digital pulse width identification is given. This circuit can be used to eliminate signals with a pulse width less than 320ns, thereby reducing noise interference. The article introduces the working principle of the identification circuit and gives a schematic diagram of the simulation waveform.

    Keywords: Digital pulse width identification, programmable device noise, ispLSI1016E

1 Introduction

Some non-coherent conventional pulse radars that were designed and produced earlier were not very capable in data processing, so the radar echoes had video accumulation after detection. In the past, this video accumulation mainly relied on the display screen and radar operation. The operator’s eyes and brains are used to identify and detect. The main disadvantage of this kind of manual observation is that the number of batches to master the target is limited and it is easy to fatigue. In response to the above shortcomings, the author added an automatic detection function to a certain type of conventional pulse radar system. One of the important contents is threshold detection, which means to compare the video signal with a threshold level to quantify it into a digital signal. Determine the presence or absence of the target, and the threshold value is designed based on the requirements of the constant false alarm rate. In addition, since it automatically detects and eliminates false targets caused by noise, this will have an impact on subsequent radar data processing. To this end, the author specifically designed a digital pulse width identification circuit based on a detailed analysis of the quantized noise level, which played a significant role in further eliminating the quantized noise level.

2 Principle and implementation of digital pulse width identification circuit

After analyzing the noise level of the comparator, it was found that it has no periodicity, appears randomly, and has a narrow pulse width. Its pulse width is generally 20ns (because the minimum output settling time of the comparator LM360 used is 20ns) to Between 200us. Since the transmit pulse width of the radar under study is 700ns, the width of the echo signal is generally greater than 500ns. Therefore, the difference in pulse width between the real echo and the noise signal can be used, and the pulse width identification circuit introduced in this article can be used to filter out digital signals with a pulse width below 320ns.

Digital pulse width discrimination circuits can be implemented through programmable devices. The designed circuit uses ispLSI1016E-80LJ from Lattice Company. Features of this device are as follows:

●Contains 2000 logic gates:

●Contains 96 registers, 32 input and output I/O and 4 dedicated inputs;

●Input and output signals are compatible with TTL levels;

●With electrical erasure and in-system programmability.

Figure 1 is a pinout diagram of this device.

The development tool used for this device is ispEXPERT, which supports schematic and language input, can efficiently adapt the design, and can simulate functions and timing to shorten design time.

This article uses schematic diagram input to complete the circuit design. The specific digital pulse width identification circuit principle is shown in Figure 2. The circuit is mainly composed of a 16-bit serial input and parallel output shift register, a 16-input AND gate and a D flip-flop.

For digital signals with a pulse width less than 320ns, the output terminals of the shift register cannot be all "1" (high level), that is to say, there are "0" (low level). In this way, the 16-input AND gate also has a "0" output, so the D flip-flop (FD21) cannot be triggered, so that there will be no "1" output at its output.

When the high-level width of the input signal is greater than 320ns, the output terminals of the shift register are all "1", so the output after the 16-input AND gate is "1", thus triggering the D flip-flop so that its output terminal output is " 1". After the input signal passes through several 50MHz clock beats (the number of beats depends on the width of the signal), the last bit of the shift register is "0" and is output to the clear end of the D flip-flop through the inverter (here the D flip-flop The effective level of the clear terminal is "1"), at this time the flip-flop outputs "0", thus completing the signal width identification, thereby filtering out signals with a high level width lower than 320ns. And the delay time of the input and output signals is 320ns, and the delay time can be compensated in software by the subsequent data processing program.

When designing, you can increase or decrease the number of bits in the shift register as needed to filter out signals of any width. For example, if you want to filter out signals with a width less than 500ns, you need to increase the number of bits in the shift register to 25 bits.

In order to protect the correctness of the design, the Lattice Logic Simulator software tool can be used to perform logic simulation on the circuit. Figure 3 shows a schematic diagram of the simulation waveform.

As can be seen from the figure: there are 5 pulses with a pulse width less than 320ns in the input signal. These pulses will be considered as noise interference. After passing through the pulse width discriminator, all 5 pulses will be filtered out, while the input signal Signals with a width greater than 320ns will not be lost, but the delay time will be increased.

3 Conclusion

After applying this digital pulse width identification circuit designed using iSPLSI 1016F to radar video quantization, it greatly reduces noise interference, reduces the generation of false targets, enhances the credibility of the target, and thereby increases the speed of radar data processing. Because the circuit is implemented by programmable devices, the overall structure is compact, highly reliable, and highly practical.