FPGA Implementation of 10G Ethernet Optical Interface

1 Overview

As people's requirements for the abundance, timeliness and convenience of communication information become higher and higher, it is becoming more and more important to be able to obtain the required information anytime, anywhere, conveniently and timely. In 2002, IEEE passed the 10 Gb/s Ethernet standard - IEEE 802.3ae[1]. As a major upgrade of traditional Ethernet technology, 10G Ethernet increases the transmission rate by 10 times based on the original Gigabit Ethernet technology to meet people's requirements for mobile communication services.

In January 2009, domestic 3G licenses were officially issued, marking the arrival of the 3G era in my country. In order to adapt to the development of mobile communications, major operators have launched large-scale 3G mobile communication network construction; and the core of mobile communication network construction is base station construction, which is also the most expensive. In addition, the performance of base stations is also a determining factor in the quality of mobile communication services. Therefore, while operators are constantly seeking new ways to improve the quality of communication services, they are also working hard to reduce the cost of communication network construction. Distributed base stations have the advantages of low cost, strong environmental adaptability, and convenient engineering construction, thus representing the basic trend of the next generation of base stations.

The core of distributed base stations is to separate the traditional macro base station baseband processing unit BBU and the radio frequency remote unit RRU, and the two are connected by optical fiber. When the network is deployed, the BBU is placed centrally, and its capacity is large, which realizes the conversion between capacity and coverage; the RRU is placed on the roof, and its environmental adaptability is strong, and multiple RRUs can share BBU baseband resources, saving baseband investment. In order to achieve more effective intercommunication between base stations and repeaters, the five major groups of Ericsson, Huawei, NEC, Nortel Networks and Siemens jointly developed the CPRI interface protocol. The standard protocol of this interface has become one of the public available indicators.

2 Brief Introduction of CPRI Protocol[2]

The CPRI (Common Public Radio Interface) protocol defines two protocol layers - the physical layer (L1) and the data link layer (L2). The CPRI interface is an internal data interface between REC (Radio Equipment Control) and RE (Radio Equipment) and between two REs; there are three different information flows (user platform data flow SAPIQ, control and management platform data flow SAPCM and synchronization platform data flow SAPS) transmitted through the CPRI interface.

3 FPGA implementation of CPRI protocol transmission solution

3.1 Basic plan

There are two solutions to implement CPRI protocol transmission using FPGA.

(1) Option 1

RocketIO transceiver FPGA implements CPRI protocol optical fiber communication [3]. RocketIO transceiver is a dedicated serial communication module integrated by Xilinx on Virtex2Pro chips and above series chips. It does not occupy other FPGA resources when in use. In Virtex5 series FPGA, RocketIO is called GTP.

The advantages of this solution are that the circuit board structure is compact, which is convenient for PCB board wiring and has high system anti-interference ability. In addition, the parameter setting is convenient, which is conducive to system debugging. Each Virtex5 FPGA chip contains multiple GTP transceivers, and 10 Gb/s high-speed transmission can be achieved by using 4 GTPs. Each GTP core contains a receive link and a transmit link[45].

(2) Solution 2

Special chips for serial-to-parallel conversion are used, such as TLK2501 produced by TI and SCAN25100[67] designed by National Semiconductor. Among them, SCAN25100 has the most complete functions, including 8b/10b encoding and decoding, high-speed serial-to-parallel conversion, lock detection, CPRI signal and frame loss detection. The chip has high-precision delay calibration measurement circuit, clock management and signal conditioning functions.

3.2 Specific Implementation

The transmission rates supported by SCAN25100 are 2.4576 Gb/s, 1.2288 Gb/s and 0.6144 Gb/s; the transmission rates supported by TLK2501 are 1.5 to 2.5 Gb/s. If a dedicated serial-to-parallel conversion chip is used, in order to achieve a rate of 10 Gb/s, four dedicated chips must be used, which increases the wiring difficulty and circuit board area of ​​the PCB board, which is not conducive to circuit design.

Figure 1 Ethernet optical interface structure

This paper adopts the first design scheme to complete the 10 Gb/s CPRI high-speed data transmission design. As shown in Figure 1, the Ethernet optical interface consists of 4 parts: 10GE optical interface, PHY transceiver, clock module, and FPGA. Among them, the 10GE optical interface and PHY transceiver are the hardware devices to realize the 10G Ethernet optical interface; the FPGA part is the core of this design, using the Virtex6 chip of Xilinx.

10GE optical interface: Optical fiber module, composed of optoelectronic devices, functional circuits and optical interfaces, including two parts: transmitting and receiving. The transmitting part is: the electrical signal with a certain bit rate is input, and after being processed by the internal driver chip, it drives the semiconductor laser or light-emitting diode to emit a modulated optical signal with a corresponding rate. The receiving part is: the optical signal with a certain bit rate is input into the module and converted into an electrical signal by the optical signal tube, and then outputs the electrical signal with the corresponding bit rate after passing through the preamplifier [7]. According to the results discussed in reference [7], the circuit structure designed in this paper uses the XFP (10 Gigabit Ethernet Small Package Pluggable Transceiver) optical module, and the interface with the circuit board uses a 10 Gb/s serial circuit interface, which is only responsible for completing the conversion of optical/electrical signals. The advantages are small size, low power consumption and easy multi-port integration.

PHY transceiver: Physical layer chip, whose main function is to provide Ethernet access channel. This module synthesizes 4 3.125 Gb/s data streams transmitted from FPGA into 12.5 Gb/s data stream and transmits it to the optical module; and divides the 12.5 Gb/s data stream transmitted from the optical module into 4 links and transmits it to FPGA at 3.125 Gb/s. In this data stream transmission, since FPGA performs 8b/10b encoding and decoding on the data, the effective bit rate is 10 Gb/s, which can meet the design requirements of this article and realize 10G Ethernet data stream transmission.

Clock module: The clock module uses an active crystal oscillator with an output frequency of 61.44 MHz to provide the system with a clock. Since the data transmission rate of each data link is 3.125 Gb/s, the GTP core has very high accuracy requirements for the reference clock, so the system selects a high-precision differential clock as the reference clock. In this system design, the reference clock of the GTP core does not use the clock provided by the DCM (Digital Clock Manager). Because during high-speed data transmission, the DCM will introduce some unpredictable clock jitter, which will be input into the GTP core along with the reference clock, causing bit errors. Usually, an external differential crystal oscillator source is used, and the output signal of the global clock buffer is used as the reference clock of the GTP. During the data transmission process, the clock is generated by the DCM inside the GTP as the clock source of RXUSRCLK, RXUSRCLK2, TXUSRCLK, and TXUSRCLK2, thereby eliminating clock jitter and maintaining synchronization during data transmission [89].

FPGA part: Its main functions include functional functions and configuration monitoring functions. In this solution, the function of FPGA is mainly to complete the 8b/10b encoding and decoding of data, high-speed serial-to-parallel conversion, and the framing, deframing, synchronization, transmission data multiplexing/decomposition and other operations of the CPRI protocol. The control function of FPGA is mainly for optical interface modules and PHY modules. For optical interface modules, since XFP provides a two-wire serial interface, it can realize data diagnosis functions and monitor various parameters of optical modules in real time, so FPGA can realize real-time monitoring of its working status. For PHY modules, FPGA controls the working mode of the module and detects the working status of the module through the SMI interface. [page]

4 Design Verification

4.1 Design Verification Method

In order to verify the correctness of the circuit design, the reliability of the circuit was tested. A pseudo-random number sequence (PRBS) generation and detection circuit was added to the FPGA design system. Since the IP core GTP in Xilinx's Virtex6 chip contains a pseudo-random number sequence (PRBS) generation and detection circuit, this paper uses its internal circuit to automatically generate PRBS and pass it through the entire 10 Gb/s Ethernet high-speed data link. Finally, its detection circuit is used to check whether there is a bit error in the data transmission. The test plan is shown in Figure 2. There are 4 GTX cores in the FPGA for generating and detecting PRBS, each corresponding to a 2.5G link.

Figure 2 Test plan

According to the user instructions for GTP provided by Xilinx [9], the values ​​of the signals TXENPRBSTST0, TXENPRBSTST1, RXENPRBSTST0, and RXENPRBSTST1 are set to 01, and the value of the signal INTDATAWIDTH is set to 1. The type of pseudo-random number sequence generated is PRBS7. The polynomial for generating the PRBS7 sequence is 1+X6+X7, and the data length is 128, which can verify the data after 8b/10b conversion. The value of the signal RXPRBSERR is set to 1 to detect whether there are bit errors in the data during high-speed data transmission. The values ​​of the signals PRBS_ERR_THRESHOLD0 and PRBS_ERR_THRESHOLD1 are set, which means the threshold of the total number of errors in the PRBS cycle detection, to control the signal RXPRBSERR (0,1). The signal RXPRBSERR indicates that the total value of data errors detected in the PRBS cycle test exceeds the threshold set by PRBS_ERR_THRESHOLD, and the signal becomes 1. The generated PRBS sequence is looped back through the transmission link and the external link, and then transmitted to the receiving link. After corresponding processing, it reaches the PRBS detection circuit to verify the correctness of the data. Among them, the external link loopback mainly refers to connecting the two ends of an optical fiber to the receiving and transmitting ends of the 10G optical interface respectively, so that the data itself is looped back in the design system.

4.2 Verification Results

The high-speed transmission data of the system is verified under the normal temperature environment of the laboratory. The verification is divided into two parts. The first part is to use the software tool Chipscope developed by Xilinx to capture the data received and sent inside the FPGA for comparison to verify whether the designed system can achieve the required functions. The results captured by Chipscope are shown in Figure 3. Signals program_after_data0~3 are the data output by the PRBS generation module after being processed by the functional module. Signals RX0_PRBSERR0 and RX0_PRBSERR1 are RXPRBSERR0 and 1 in the PRBS detection module in the first link. It can be seen from the figure that their values ​​are 1, that is, the error count of the 0th data link in the system does not exceed the value of the threshold PRBS_ERR_THRESHOLD. As can be seen from the figure, the values ​​of signals RX1_PRBSERR0, 1, RX2_PRBSERR0, 1 and RX3_PRBSERR0, 1 are all 0, so the error counts of the four data links of the system do not exceed the threshold.

Figure 3 Chipscope system test results

The second part is to use a high-frequency range oscilloscope to capture the data output by FPGA to the PHY chip to detect the signal quality of the system transmission. The data transmission eye diagram tested by the oscilloscope is shown in Figure 4. Due to the same configuration of the 4-way 2.5G transmission link and limited space, only the eye diagram of the 0th transmission data is listed. The bit error rate (EyeBER) of the eye diagram transmitted by this system can reach 10-45, and the eye height is about 600 mV.

Figure 4 High-speed data transmission eye diagram

Conclusion

Through repeated verification and long-term continuous testing, the test results prove that the design can effectively and correctly achieve 10 Gb/s high-speed data transmission, and the bit error of the transmitted data does not exceed the threshold, which further proves the reliability and stability of the design system. The use of the RocketIO interface in the FPGA to design 10 Gb/s optical fiber transmission greatly enhances the flexibility of optical fiber transmission design, and can be used in a variety of situations and occasions for high-speed signal transmission by modifying the FPGA code.