Design of Automatic Data Acquisition System with Verilog HDL

With the advent of the digital age, the application of digital technology has penetrated into every aspect of human life.

The development of digital systems has benefited greatly from the development of devices and integrated technology. The prediction of the famous Moore's Law has also been confirmed in the development of integrated circuits. The design concepts and methods of digital systems have undergone profound changes in this process. From electronic CAD, electronic CAE to electronic design automation (EDA), as the complexity of design continues to increase, the degree of automation of design is getting higher and higher. At present, EDA technology, as a general platform for electronic design, is gradually developing towards supporting system-level design; the design of digital systems has also developed from graphical design methods to hardware description language design methods. Programmable devices are widely used in the field of digital system design, which not only shortens the system development cycle, but also utilizes the field programmable characteristics of the device to dynamically configure or program the device according to the requirements of the application, and easily complete the addition and modification of functions.

In the development of modern industry, real-time measurement and control systems are widely used, which puts higher requirements on high-speed digital signal processing systems. Because it involves a lot of calculations, a large number of DSP devices are used to improve the operation speed. The data acquisition system is one of the core parts of the entire system. The traditional method is to use MCU or DSP to control the analog/digital conversion of data acquisition through software, which will inevitably frequently interrupt the operation of the system, thereby weakening the data computing ability of the system, and the speed of data acquisition will also be limited. Therefore, the DSP+CPLD solution is considered to be one of the best solutions for digital signal processing systems, which controls analog/digital conversion and data storage by hardware, thereby maximizing the signal acquisition and processing capabilities of the system.

1 System Overall Plan

The data acquisition system is a part of the signal processing system based on DSP, and the block diagram is shown in Figure 1. This digital signal processing system is used in the application research of random resonance theory in weak signal detection. The whole system consists of signal amplification, signal filtering, signal sampling, high-speed digital signal processing, and high-speed data transmission interface with the host computer. Among them, signal amplification is to condition the input signal to meet the sampling requirements; signal filtering is to prevent the signal from producing "aliasing phenomenon"; signal sampling is to complete the digitization of analog signals; high-speed digital signal processing is to complete various algorithms based on the establishment of random resonance model; the high-speed data transmission interface with the host computer is to meet the real-time nature of signal detection, and transmit the data processed by DSP to the computer for further processing. The automatic state machine designed based on Verilog HDL controls the A/D conversion by hardware and automatically stores data in FIFO. The sampling frequency is determined by the output clock of the DSP system. When the sampled data reaches one frame, the FIFO applies for interruption to the DSP, and the DSP system starts DMA to complete data reading. During this period, data acquisition is not interrupted, thereby realizing continuous real-time data acquisition and real-time data processing. The data acquisition system is composed of A/D chip MAX196, logic control chip EPM7128, and FIFO chip CY7C425. The control logic is described in Verilog HDL language, and simulation and actual verification are carried out.

2 Hardware Circuit Design

2.1 A/D conversion chip

The system A/D conversion is implemented by the MAX196 chip. The features of MAX196 are:

①12-bit A/D conversion accuracy, 1/2 LSB linearity;

②Single 5V power supply;

③The software selects the analog input range, which are: ±10V, ±5V, 0~5V, 0~10V;

④6 analog input channels;

⑤6μs conversion time, 100ksps sampling rate;

⑥Internal or external sampling control;

⑦Internal or external clock controls conversion.

In the control word of MAX196:

①A2A1A0 is the channel selection word: 000~101 represent channels 0~5 respectively;

②BIP and RNG are input range and polarity selection;

③ACQMOD: sampling control mode, 0 is internal control sampling, 1 is external control sampling;

④PD1 and PD0 are for clock and power saving mode selection.

The timing of the internal conversion mode is shown in Figure 2. When the control word containing channel selection, range selection, and polarity selection is written to the MAX196, the initialization of the A/D conversion is completed. The ACQMOD bit of the control word is used to select the internal conversion mode and the external conversion mode. When the control word with the ACQMOD bit of 0 is written, the internal conversion mode will be started. Here, the internal sampling mode is used. One conversion requires 12 clock cycles, and the conversion cycle is determined by the internal clock of the chip. Writing a write pulse (WR+CS) can start a conversion. When a new control word is written during the A/D conversion, the conversion will be terminated and a new sampling cycle will be started. The A/D conversion is completed, and the output low-level signal INT is valid. The signal RD reads the A/D conversion result and resets the INT signal. A complete conversion cycle ends.

2.2 Data Buffer

The data collected by the system is often placed in the data buffer. The data buffer area requires both an interface with the A/D chip and an interface with the system DSP to improve the data throughput, so dual-port RAM or FIFO is often used. Since FIFO does not require address addressing, in order to simplify the control signal, this module uses the FIFO chip CY7C425 as the data buffer area. FIFO memory allows data to be written and read independently of the data rate, and is always read out in the order of writing. The memory is judged to be full or empty based on the Full and Empty flags. The FIFO chip can expand the data width and storage depth without adding additional time delay. When the write signal (W) is low, the write operation occurs, and when the read signal (R) is low, the read operation occurs. The results of the A/D conversion are continuously stored in the FIFO through the write operation. When the FIFO is full, the Full flag is valid, and an interrupt is requested to the system. The DSP responds to the interrupt and immediately starts DMA to read the data in the FIFO. When the data is empty, the Empty flag is valid and the DSP stops the read operation. Two CY7C425 chips are used to expand the 18-bit 1024-word high-speed asynchronous FIFO memory. The data processing speed reaches 50MHz, which can realize high-speed data writing and high-speed reading. The FIFO asynchronous reading and writing timing is shown in Figure 3.

2.3 State Machine Module

The state machine (FSM) completes automatic A/D conversion and data storage. The control chip is EPM7128SQC100. The state machine is driven by the system clock and generates RD, WR, and INT signals. The state machine can run continuously, continuously write command words to start A/D conversion, and then read the A/D conversion results and write them into FIFO at the same time.

When reset, a write pulse WR is generated. The chip MAX196 latches the external input command control word at the rising edge of WR and starts A/D conversion. When the A/D conversion is completed, the chip INT becomes low level, and at the rising edge of the next clock, RD becomes low level, and data is output on the data bus. When the RD signal is valid at a low level, the INT signal becomes high level, and at the rising edge of the next clock, the RD signal becomes high level, and the data is latched into the FIFO at the rising edge of RD. After the RD signal returns to a high level, the WR signal becomes low level, and the next conversion starts again.

3 Verilog HDL Description of the System

In the design of electronic systems, a top-down design approach is generally followed to design, describe and simulate the system. Considering the universality and portability of modules, HDL languages ​​are often used to describe digital systems, such as Verilog HDL, VHDL, AHDL, etc. Among them, Verilog HDL has the advantages of clear structure, concise grammar, powerful functions, high-speed simulation and multi-library support. It is used by nearly 90% of semiconductor companies and has become a powerful design tool.

3.1 Describing the MAX196 in Verilog HDL

The MAX196 module is described by Verilog HDL program. The module can be used for the simulation of the acquisition system to verify the correctness of the state machine design. The module mainly has three input signals and one output signal, which are consistent with the control signal of the chip. The program description is as follows:

module adc(reset, rd_adc, wr_adc, int_adc);

input reset, rd_adc, wr_adc;

output int_adc;

reg int_adc;

always @(posedge wr_adc or negedge rd_adc or negedge reset)

begin

if(!reset)int_adc=1;

else if(rd_adc==0)begin int_adc=1;end

else begin #10 int_adc=0;end

end

endmodule

3.2 Describing Automatic State Machines Using Verilog HDL

The automatic state machine has three input signals and two output signals. The input signal clk is output by the DSP system to control the sampling speed, the reset signal resets the automatic state machine, int_adc is the response signal of the end of the A/D chip conversion; the output signals rd_adc and wr_adc control the start of the A/D chip conversion and the reading of data, as well as control the FIFO to write data into the FIFO. The program description is as follows:

module fsm(int_adc, clk, reset, rd_adc, wr_adc);

output rd_adc，wr_adc;

input int_adc, clk, reset;

reg rd_adc，wr_adc;

reg[1：0]present;

parameter reset_ad=2'h0, start_ad=2'h1, wait_ad=2'h2, read_ad=2'h3;

always @(posedge clk or negedge reset)

if(~reset) begin present=reset_ad;rd_adc=1;wr_adc=0;end

else

begin

case(present)

reset_ad：if(rd_adc)

begin present=start_ad;wr_adc=1;end

start_ad：if(~int_adc)

begin present=wait_ad;rd_adc=0;end

wait_ad：if(~rd_adc)

begin present=read_ad;wr_adc=0;end

read_ad：if(~int_adc)

begin present=reset_ad;rd_adc=1;end

endcase

end

endmodule

3.3 Data Acquisition System

The MAX196 module and the state machine module form a high-level module - the automatic sampling system. The combination of modules is realized through the calling of module instances and port mapping statements. The output signal int_adc is specially set to make the simulation waveform clearer. The program description is as follows:

module simuadc(clk, reset, rd_ad, wr_adc, int_adc); //system module

output rd_adc, wr_adc, int_adc;

input clk，reset;

reg rd_adc,wr_adc,int_adc;

adc adcmax196(reset,rd_adc,wr_adc,int_adc); //A/D chip module

fsm fsmdsp(int_adc, clk, reset, rd_adc, wr_adc); //state machine module

endmodule

3.4 Simulation Graphics

Figure 5 is a timing simulation diagram of the acquisition system. CLK is the system external clock, which is used to control the sampling frequency; RESET is connected to the external reset signal, which can control the starting time of sampling; WR_ADC, RD_ADC, and INT_ADC of MAX196 are connected to the control pins of the logic chip EPM7128 respectively. The simulation diagram shows that after reset, as long as there is a CLK clock output, the A/D conversion will continue, and the conversion data will be stored in FIFO in sequence. When the FIFO is full, an interrupt request is sent to the DSP, and the DSP responds in time and starts DMA to read the value in the FIFO at high speed. Since the DSP reads in fast enough, the A/D conversion does not need to pause, thereby realizing real-time sampling and real-time processing. The automatic acquisition system proposed in this paper uses CPLD chip, and uses hardware description language to design the automatic state machine to realize hardware control data acquisition and storage. At present, the acquisition system is applied to the DSP application board, which eliminates the time for DSP to monitor the A/D chip, so that the signal processing system can efficiently complete the research of complex stochastic resonance systems.