Design of intelligent building video image digital compression system

　　Intelligent buildings are the product of a combination of modern architecture and high-tech information technology. In 1984, the world's first smart building was built in Hartford, Connecticut, USA. The following year, a smart building was built in Tokyo, Japan. As a result, smart buildings attracted the attention of countries around the world. Currently, there is an upsurge in building a large number of smart devices in our country, in which the design of image signal processors is crucial. The traditional monitoring system with analog electronic technology as the core requires a large amount of video tapes to directly record the images due to the large amount of image information transmitted by the camera, making it difficult to meet the needs of computer network transmission and information sharing. Using relevant coding technology to compress images and achieve real-time storage and transmission in the system is an urgent requirement for modern smart buildings. However, the methods used in image compression are generally complex and require a large amount of computing workload. It is difficult to achieve real-time image compression by software alone. Hardware is generally used to increase the computing speed to meet real-time image compression. It is under this circumstance that this paper proposes an improved video image wavelet compression algorithm, designs a hardware platform based on the high-speed digital processing chip DSP-C6201, and programs the improved wavelet compression algorithm on this platform to realize a smart building Unequal resolution video image compression for surveillance systems.

　　1 Image compression technology[6]

　　Among the many image compression algorithms that have emerged in recent years, the most promising ones are fractal coding based on block classification and zero-tree coding based on wavelet transform. The theoretical basis of fractal compression is the iterative function system (IFS) theory and collage theorem proposed by Barnsley et al. It essentially finds the smallest number of compression affine transformations with the best matching, and takes out its parameters. If the complexity of its parameters is lower than that of the original image, compression is achieved. Another compelling compression algorithm is zerotree coding based on wavelet transform. The total amount of coefficient data generated after the image is transformed by wavelet is equal to the data amount of the original image. That is, the wavelet transform itself does not have a compression function. The reason why it is used for image compression is because the generated wavelet coefficients have energy concentration and are important. Characteristics such as the clustering of coefficients, the similarity between component coefficients, and the attenuation of component coefficient amplitudes are suitable for classification compression. The zero-tree coding scheme based on up-wave transformation makes full and effective use of the frequency distribution characteristics of wavelets, does not produce obvious block effects like fractals, is easy to implement in software and hardware, and is suitable for the compression of many types of images. A typical representative of this type of algorithm is the embedded zerotree coding (EZW) proposed by Shapiro. However, an obvious shortcoming of the Shapiro scheme is that coefficients at different levels are given equal consideration when judging important coefficients. Based on the Shapiro scheme, this paper proposes an improved wavelet compression scheme based on PSWTC (priority set wavelet tree coding) to overcome this shortcoming and solve the method problem of judging the importance of wavelet coefficients of different sizes and levels. The distribution of PS coefficients of PSWTC results has obvious regularity, with fewer high-level ones and more low-level ones, showing a pyramid distribution, which shows that PSWTC well implements the basic principles of the zero-tree coding scheme. Compared with EZW, PSWTC has less computational complexity, takes up less storage space, takes less time, and is easy to achieve rapid compression, overcoming the time-consuming and labor-intensive shortcomings of traditional wavelet image coding [4][5]. The specific steps of the PSWTC algorithm are: (1) Ignore the low-frequency coefficients for the time being, and set all the highest-level nodes as coefficients to be divided to form a set of coefficients to be divided. (2) Set the threshold, and set the initial threshold to T=Tmax=2%26;#215;exp{「log2Max「| All wavelet coefficients. (3) Based on gate root comparison, judge the importance of the coefficient to be divided and output Sn, n=1. If it is important, output 1, if it is not important, output 0. The importance of the coefficient is determined by the importance of its wavelet pair set. ( 4) Add all important coefficients to the priority set (priority, PS for short) Xi, i=1 in zigzag order, delete them from the coefficients to be moved, and fill in their children in zigzag order. (5) Threshold Reduce the number of tasks, T=T/2, jump to step 3, and gradually form the priority set Xi, i=2, 3... until the threshold reaches a predetermined minimum threshold value or there is no node in the coefficient to be divided. On this basis The image compression method in the order of wavelet transform → coefficient classification → entropy coding is given above.

　　2 Hardware design

　　The analog video signal is converted into a digital video signal after high-speed A/D sampling. The digital video signal consists of two signals, the odd field signal and the even field signal. The odd field signal and the even field signal are image compressed according to the above-mentioned improved wavelet compression scheme. Using TI's C6201 fixed-point processor with multi-processing units, the processor can use a working frequency of 50MHz or 100MHz, which is increased to 200MHz after internal frequency multiplication, and can complete 1.6G operations per second. It contains a CPU with ultra-long instruction word processing capabilities and 8 functional units, so it can execute 8 instructions in one clock cycle. The chip's computing power is significantly improved, coupled with its good external RAM interface and 16-bit host interface And the four-channel DMA function makes it the first choice chip for high-speed computing [2][3]. The hardware structure of the system [1] is shown in Figure 1. This system plans to use three C6201s, one is responsible for the compression and storage of odd field images, one is responsible for the compression and storage of even field images, and one main C6201 is responsible for the storage, judgment and communication of one frame of compressed images. Its working principle is as follows: (1 ) The video signal to be processed is first sent to the A/D processing module. The A/D module consists of a video synchronization separation circuit, a DC recovery circuit, a phase-locked loop clock circuit and a high-speed video analog/digital converter. The video signal to be processed passes through the synchronization separation circuit to separate the horizontal and vertical synchronization signals and the odd and even field signals, and sends the horizontal and vertical synchronization and odd and even field signals to the CPLD as the time reference signal. At the same time, the video image signal to be processed restores its DC component through the DC recovery circuit, and then is converted into a digital signal through analog-to-digital conversion. (2) The converted digital signal is first buffered by the dual-port memory. CPLD generates write addresses and read and write control signals for the dual-port RAM (DPRAM) through logic synthesis, so that the A/D converted data is stored in the dual-port RAM as required. Then they are read by two C6x slices (Odd-C6x and Even-C6x). The odd field signal is read by Odd-C6x, and the even field signal is read by Even-C6x. The dual-port RAM uses a 16-line cache, and the two C6x chips (Odd-C6x and Even-C6x) read every 16 lines. When the dual-port RAM stores 16 lines, CPLD sends an interrupt signal to Odd-C6x or Even-C6x, and then Odd-C6x or Even-C6x reads the 16 lines of stored data. (3) When the Odd-C6x or Even-C6x processor receives the interrupt signal from the CPLD, it immediately responds to the external interrupt and gives an interrupt response signal to the CPLD. The CPLD uses logical operations to combine the data between the Odd-C6x or Even-C6x and the DPRAM. When the buffer is turned on, the DMA controller inside Odd-C6x or Even-C6x reads the data in the corresponding DPRAM into Odd-C6x or Enen-C6x in DMA mode and compresses the image data, and stores the compressed result into SBSRAM. , and transfer some compression parameters to Main-C6x for further analysis and slices. The hardware structure of the entire system is shown in Figure 2. 　　

　　This hardware system can collect and compress high-resolution 768%26;#215;576 video images in real time. The maximum data processing speed of the compression card is 200Mbps. If multiple cameras collect and compress data at the same time, a multi-channel compression single-machine parallel array structure can be used. Before image compression, the target can also be roughly detected and recognized according to the user's requirements, and only the area of ​​interest can be compressed, or compression with different compression ratios can not only improve the compression ratio, but also retain as much sense as possible. Image details of areas of interest. TMS320C6201 is used as a high-speed signal processor and an efficient wavelet algorithm is used to digitally compress the collected video signals, which achieves good results.

　　Experimental results show that its compression effect is significantly improved compared to the EZW algorithm. The PSNR of the restored image is increased by 0.22 to 1.01dB. The maximum grayscale error is smaller by 2 grayscales on average. The restored results are clearer and the distortion is smaller. It is significantly better than SPIHT in the case of large compression ratio (SPIHT compression method is an improvement of EZW, which has improved both compression speed and image recovery quality, and is one of the algorithms with the highest peak signal-to-noise ratio for image recovery so far). The digital monitoring system thus developed has been successfully used in a smart building. This digital monitoring system has the advantages of simple operation, timely alarm, fast playback, clear image, and high compression ratio. At the same time, the system has the advantages of strong independence, high confidentiality, and high compression ratio. At the same time, the system has the characteristics of strong independence, high confidentiality, simultaneous capture of multiple channels, and high speed of 25fps/s for each channel during preview. It provides all-day time settings, and the 60G standard hard drive can store a week's worth of data. The successful development of this system laid a solid foundation for the digitalization of the monitoring system.