Application of ferroelectric memory FM18L08 in DSP system

　　1 Introduction

　　Ferroelectric memory (FRAM) is a power-down non-volatile memory launched by Ramtron in recent years. It combines high performance and low power consumption operation and can save data without power supply. FRAM overcomes the shortcomings of long writing time and low erase and write times of EEPROM and FLASH, and its price is much lower than non-volatile lithium battery SRAM of the same capacity. It has been widely used in subway systems, meter reading systems and IT industries.

　　TMS320VC5402 (hereinafter referred to as C5402) is a cost-effective 16-bit fixed-point digital signal processor (DSP) launched by Texas Instruments (TI) in the United States. The operating rate can reach 100MIPS. Its rich internal resource configuration provides users with the ability to construct systems. It is very convenient and has been widely used in communications, electronics, image processing and other fields. However, C5402 is a RAM type device and cannot retain any user information after power off, so the user needs to put the program code in non-volatile memory. When the system is powered on, it will be stored externally by executing the self-bootloader program. The code in the media is loaded into the C5402's high-speed on-chip memory or the extended memory in the system. After successful loading, the code is automatically executed and self-starting is completed. Based on practical experience, this article introduces the characteristics of a parallel interface ferroelectric memory FM18L08, and also analyzes the characteristics of the C5402 parallel bootloading mode, and proposes a design scheme based on the ferroelectric memory FM18L08 and C5402 interface, realizing the implementation based on The DSP offline independent operation system design in parallel boot loading mode has been successfully applied to a voice door lock system.

　　2 FM18L08

　　FRAM Features At the heart of Ramtron's FRAM memory technology are tiny ferroelectric crystals integrated into the memory cells so that they operate like fast, non-volatile RAM. When an electric field is applied to a ferroelectric crystal, the central atom moves in the direction of the field. When the electric field is removed, the central atom remains stationary and the state of the memory is saved. FRAM memory does not need to be refreshed regularly and the data is saved immediately after power off. FM18L08 is a FRAM with a storage capacity of 32k╳8bits launched by Ramtron in recent years. Its main features are as follows: 3.0-3.65V single power supply; parallel interface; available in SOIC and DIP packages; low power consumption, quiescent current less than 15uA. The read and write current is less than 10mA; non-volatile, data can be saved for 10 years after power failure; unlimited reading and writing times. The pin structure of FM18L08 is shown in Figure 1: /CE: Chip select/WE: Write enable/OE: Output enable A0-A14: Address terminal DQ0-DQ7: Data terminal VDD: Power supply VSS: Ground

　　3 C5402 parallel boot loading mode design

　　3.1 Program boot loading mode type of C5402 system:

　　C5402 provides the following boot load mode types: ① HPI (host interface) boot load mode The program code to be executed is loaded into the DSP on-chip memory by the external processor through the host interface bus. When the external processor changes the contents of the starting address of the loaded code (C5402 chip address 007FH), it starts executing the boot loader. ② The 8-bit/16-bit parallel boot loader mode boot loader reads the data stored in the external data storage unit through the external parallel interface bus. The data in the external data unit is stored in a certain format, and its information includes: each segment of program code to be loaded, the length of each segment of program code, the target address where each segment of program code is stored, the entry address of the program code, and other configuration information. ③ 8-bit/16-bit standard serial port boot loader mode The boot loader reads the data stored in the external data storage unit through the multi-channel buffered serial port (McBSP) set to standard mode. Multi-channel buffered serial port 1 (McBSP1) supports 8-bit serial reception mode, and multi-channel buffered serial port 0 (McBSP0) supports 16-bit serial reception mode. ④ 8-bit serial EEPROM boot loader mode The boot loader reads the data stored in the external data storage unit through a serial EEPROM. In this way, the EEPROM is connected to McBSP1 set to SPI operating mode. ⑤I/O boot loader mode boot loader reads data through the I/O port with the external parallel interface bus address 00H. This external parallel port interface bus uses an asynchronous handshake protocol (using the XF and BIO pins of the C5402) to enable data transfer speeds as required by the external memory device.

　　3.2 C5402 parallel boot loading mode design

　　When C5402 works in microcomputer mode (MP/MC=0), it will automatically run the Bootloader program after power-on, and follow the HPI boot loader mode, serial EEPROM boot loader mode, parallel boot loader mode, standard serial port boot loader mode I/O port Sequential loop detection of boot loader modes to determine which boot mode to execute. For digital signal processing systems with C5402 as the core, the parallel boot loader mode is considered to be the most suitable. Because the HPI boot loader mode, standard serial port boot loader mode and I/O port boot loader mode are only applicable to multi-processor systems where other processors provide running code for the C5402, the serial EEPROM boot loader mode is only supported by the price range. High SPI port EEPROM, and the parallel boot loading mode can use many types of parallel EEPROM and Flash, some of which are relatively low-priced and relatively simple to operate, so the parallel boot loading solution is the best choice.

　　In order for the C5402 to effectively boot the program in the external FRAM to the on-chip RAM, a boot table needs to be compiled. The boot table is located in the 4000h~FFFFh segment of the data space. The content of the boot table includes the following aspects: (1) The identification of the boot mode; (2) The target first address where the program is stored; (3) The entry address for program execution; (4) User program code; (5) User program block length. The boot table structure is shown in Table 1. Data area address (H) Content (H) Meaning 8000, 8001 8002, 8003 8004, 8005 8006, 8007 8008, 8009 800A, 800B 800C, 800D 800E, 800F 8010, 8011 8012, 8013... 8030, 805 3 8054, 8055… … FFFE, FFFF 08, AA 7F, FF 88, 06 00, 00 00, 80 00, 44 00, 00 00, 80 F6, BD F0, 70 … F4, 95 00, 00 … 80, 00 8-bit boot Flag SWWSR register initial value BSCR register initial value Program entry XPC Program entry address Program segment length Program storage target In boot loading mode, the boot program of the on-chip ROM in the boot table first reads the FFFFh address content of the I/O space (specified as 8000h) as the starting address of the boot table, and determines whether it is 8 by identifying the boot flag in the starting address of the boot table. Bit parallel or 16-bit parallel boot mode. If the boot flag is 10AAh, it is a 16-bit parallel boot mode; if the boot flag is 08AAh, it is an 8-bit parallel boot mode. When no valid boot identifier can be read from the I/O space FFFFh address, the on-chip ROM boot program reads the contents of the data space FFFFh as the starting address of the boot table. It is also determined whether it is an 8-bit parallel or a 16-bit parallel boot mode by identifying the boot flag in the starting address of the boot table. When the EPROM data bit width is 8 bits, the content of the data space FFFFh address (low byte) and the content of the FFFEh address (high byte) must be read as the starting address of the boot table. The implementation circuit of 8bit parallel boot loading is shown in Figure 1. Among them, A15 passes through the NOT gate and /MSTRB phase or to prevent the C5402's internal 16K DARAM (0000H-3FFFH) from conflicting with the external FRAM. At the same time, it corresponds to the boot table setting of the parallel boot loading mode.

　　Figure 1 Hardware system schematic diagram

　　4System software design

　　In this system, the core of software programming is to write data into FM18L08 FRAM according to a specific format. The design method of the software system is introduced in detail below. In TI's software development tool CCS (Code Composer Studio), the target files created by the assembler and connector adopt the COFF (Common Object File Format) format, and the code and data are organized and designed by Section. First download the program to the on-chip DARAM of the C5402 of the hardware system through CCS, then run the program to write the required data and program to the FM18L08 FRAM (corresponding to 08000h-0FFFFh of DSP data addressing) according to the format in Table 1, interrupt Open the connection between the hardware system and the CCS environment, power on or reset the C5402, and you will see the lights flashing. At this time, the hardware system can run offline and independently. .mmregs .data table:.word 08aah; 16-bit boot flag.word 7fffh,8806h; SWWSR register initial value and BSCR register initial value.word 0000h,080h,00044h; program entry XPC, program entry address and program segment length.word 0000h,080h; store the target XPC and store the target address.global main .text main: stm #07fh,sp stm #0fffeh,ar1; write 80h st #080h,*ar1+ nop st #00h,*ar1 to the 07FFEh unit of FRAM ;Write 00h nop stm #table,ar1 to the 07FFFh unit of FRAM; Write the content required by the boot table to the 0000h starting unit of FRAM stm #07h,brc stm #8000h,ar2 rptb loopa ld *ar1+,a nop stl a ,*ar2+ ld a,-8,a stl a,*ar2+ loopa: nop nop stm #start,ar1; write the running program code stm #21h,brc nop ld *ar1+,a stl a,*ar2+ ld to FRAM a,-8,a stl a,*ar2+ loopb: nop nop ld #00h,a nop stl a,*ar2+ stl a,*ar2 b $ .sect "chengxu" ; Run the system program offline independently start: rsbx xf ; The light is on... ssbx Among them, the length of the code segment can be calculated in the CCS disassembly window after loading the DSP system, or it can be obtained from the image file (suffix .map) generated by the connection.

　　5 Conclusion

　　The DSP parallel boot loading solution based on ferroelectric memory FM18L08 introduced in this article can realize the design of DSP offline independent operation system without the need of a dedicated programmer, and this solution has been successfully applied to a voice door lock system middle. Experimental results show that this method has the advantages of simplifying the interface circuit, saving system resources, and being cost-effective. However, if the offline independent running system program exceeds 64K bytes, other alternative methods can only be used. This is an issue that needs to be considered when demonstrating some circuit design solutions. Author Email: zk197911@yahoo.com.cn