Digital recording system designed according to G.723 standard

　　With the rapid development of digital technology, the continuous maturity of voice signal digital processing technology [1], the widespread application of programmable devices and powerful digital signal processors (DSP), traditional analog audio and video equipment has been largely replaced by various digital equipment replaced. However, portable recording equipment is still dominated by various analog media, such as commonly used tape recorders. If the recording is to be saved in digital form, the analog recording signal should be converted into digital form data, which brings a lot of inconvenience to the preservation of the original data. Therefore, the author designed a digital recorder according to the G.723 standard. It uses ADSP-2181 as the voice processor and system controller, cancels the mechanical part and tape of the ordinary recorder, and uses a large-capacity flash memory (Flash RAM). As a digital voice data storage. The prototype has a small size, long recording time, no mechanical noise and mechanical failure, and is of great practical value.

　　1 G.723 standard introduction and system structure block diagram

　　1.1 Introduction to G.723 standard

　　G.723 is a multimedia voice codec standard formulated by ITU-T in 1996. Its typical applications include IP telephony services, H.324 video telephony, wireless telephones, digital satellite systems, Digital Multiplier Equipment (DCME), Public Switched Telephone Network (PSTN), ISDN and various multimedia voice information products. The G.723 standard transmission bit rate has two types: 5.3kb/s and 6.3kb/s, which can be switched at any time during the programming process. This standard mainly includes encoding algorithms and decoding algorithms. The principle is: parse the vocal tract model parameters from the collected speech signal, construct a synthesis filter, and use an appropriate excitation source to excite it. The parameters for encoding and transmission are mainly the parameters of the excitation source and the synthesis filter. The 5.3kb/s encoder uses algebraic code line prediction excitation (ACELP); the 6.3kb/s encoder uses multi-pulse maximum likelihood quantization (MP-MLQ) excitation. According to the transmission coding parameters, the reconfigurable excitation source and synthesis filter are decoded, and the restored digital speech signal is converted into an analog speech signal by a D/A converter. For detailed instructions on G.723 encoding and decoding, see reference [2]. 　The G.723 algorithm has a good encoding and decoding effect on speech signals, and can also process music and other sound signals. The typical input is 64kb/s (8k%26;#215;8) or 128kb/s (8k%26; #215;16) A-law or μ-law PCM sampled speech signal. One frame of speech signal is processed at a time, with 240 sampling points (30ms) per frame. At a code rate of 5.3kb/s, each frame of speech is compressed into 20 bytes for transmission; at a code rate of 6.3kb/s, each frame of speech is compressed into 24 bytes for transmission.

　　1.2 Structural block diagram of digital recording system

　　The system block diagram mainly consists of five parts shown in Figure 1.

　　AD73311 is used for A/D and D/A conversion. It integrates analog/digital and digital/analog conversion functions, and is programmable and controllable, making it extremely easy to use. ADSP-2181 is the core digital processor of the system [3], clock The frequency is 33MHz and its function is powerful; KM29N32000 is flash memory (Flash RAM), used to store compressed voice data; AT27C010 (EPROM) is used to store the program that controls the work of ADSP-2181; LCD is used to display the current work of the system state. The workflow of the system is: the analog voice signal is sampled by AD73311 and compressed by A-law or μ-law, then converted into PCM data. It is sent to ADSP-2181 through the serial port of ADSP-2181, and ADSP-2181 then encodes and compresses the data. Then it is sent to the flash memory KM29N32000 for storage; during recording and playback, the compressed data is read from the KM29N32000, sent back to the ADSP-2181 for decoding, and then sent to the AD73311 for D/A conversion to output analog voice signals. The entire process is controlled by the DSP program stored in AT27C010 and works in an orderly manner. LCD displays the current working status of the system.

　　2 Principles and interfaces of each main part of the system

　　2.1 Interface circuit and programming control of AD73311 and ADSP-2181

　　2.1.1 Interface circuit between AD73311 and ADSP-2181

　　AD73311 has A/D and D/A conversion functions. The sampling frequency is 8kHz~64kHz, which can be programmed and controlled. The sampling word length is 16 bits. The AD73311 has the characteristics of large signal-to-noise ratio, programmable input and output gain control, low operating voltage (2.7~5.5V), and dual-purpose chip. It is a very popular chip. The interface circuit between AD73311 and ADSP-2181 is shown in Figure 2. AD73311 completes the collection of analog voice signals and the playback of digital voice signals. As can be seen from Figure 2, the signal is input from VIN and the playback voice signal is output at VOUT. Connect the microphone to VIN and the speaker to VOUT. Communication with ADSP-2181 is carried out through the serial port, data is output to ADSP-2181 from the SDO pin, and ADSP-2181 data is received from the SDI pin. Sending and receiving can be performed at the same time. The clock signal is connected to the SLCK pin of ADSP-2181. When programming, you must first initialize the working status of the AD73311, set the sampling rate, input and output gain, advance time, etc., and then let it work in the data transmission mode to work normally. AD73311 has been performing A/D or D/A conversion after entering the data transmission mode. In programming control, the serial port of ADSP-2181 should always work in the receive interrupt mode, so that the rate of data transmission and reception can be consistent. To change the working mode, set the RESET pin low and then high again, so that it can be reset.

　　2.1.2 Programming of AD73311

　　AD73311 is a programmable data converter that contains five 8-bit control registers CRA~CRE, which are used to set the working status and control input and output. AD73311 interfaces with the processor through the serial port and transmits 16-bit data. It has five working modes: program mode, data mode, mixed mode, analog loop mode, and digital loop mode. The first three are normal working modes, and the last two are debugging modes, which are only used during debugging. The five working modes are controlled by four bits (CRA0~3) in the internal control register A.

　　Program mode: The AD73311 will work in the program mode after startup or reset. At this time, the data input by the AD73311 serial port will be used as a command word to initialize the internal control register group. After that, the AD73311 will enter the corresponding working mode according to the initialization command word. Before that The codeword output by the AD73311 serial port is invalid. Data mode: At this time, the AD73311 serial port outputs 16-bit data converted by A/D, and inputs 16-bit data converted by D/A. Once the AD73311 enters data mode, it can no longer obtain control information, so it will always be in this mode unless it is restarted. At this time, the hardware can use the sending and receiving frame synchronization signal synchronization method. Mixed mode: At this time, the 16-bit codeword may be a control word or data. The highest bit MSB of the codeword is used to identify whether the codeword is a control command word (MSB=1) or data (MSB=0, the lower 15 bits are valid data). In mixed mode, ADSP-2181 can timely change the operating parameters of AD73311 according to the operating conditions of the system, such as the amplification factor of the amplifier. At this time, the hardware can use the asynchronous method of sending and receiving frame synchronization signals to facilitate the independent control of ADSP-2181.

　　The AD73311 controls the sampling rate by a clock divider circuit. The clock frequency dividing circuit divides the external clock frequency MCLK input from the DMCLK pin into the internal clock frequency DMCLK through the main frequency clock factor. MCLK has five frequency options, controlled by the CRB4~6 bits in the internal control register B. DMCLK determines the sampling frequency of the AD73311, which is also the frame synchronization frequency of the AD73311 serial port. DMCLK is then divided by the serial clock frequency division factor into the serial clock frequency SCLK. DMCLK has four options, controlled by the GRG2~3 bits in the internal control register B.

　　By programming the control register D, the gain of the input and output can be controlled. The input gain IG can be adjusted between 0 and 38dB, and the output gain OG can be adjusted between -15 and 6dB. The specific programming flow chart of AD73311 is shown in Figure 3. The control program is as follows: AX0=DM(0x3fe5); {For 2181-PF0 connect with AD73311-RESET} AR=AX0 AND 0XFFFE; {PF0 pin reset} DM(0x3fe5)= AR; {RESET AD73311 to program} NOP; {Delay} NOP; NOP AX0=DM(0x3fe5); AR=AX0 or 0X0001; {2181-PF0 SET} DM(0x3fe5)=AR; {ready to program} ax0=0x82f9 ; {Write control register CRC, 5V power supply, enable ADC and DAC} tx0=ax0; IDLE; ax0=0x811b; {Write control register CRB, divide frequency, set 8K sampling rate} tx0=ax0; IDLE; ax0=0x8320; {Write the control register CRD, the output input gain is 0} tx0=ax0; IDLE; ax0=0x8400; {Write the control register CRE, the DAC delay is 0} ax0=ax0; IDLE; ax0=0x8001; {Write the control register CRA, Enter data transmission mode} tx0=ax0; IDLE; 2.2 Interface circuit between flash memory and ADSP-2181 The flash memory uses KM29 N32000 produced by Samsung Company of South Korea, with a capacity of 4M%26;#215;8=32Mbit, divided into 512 blocks , each block has 16 pages, each page is 528 bytes. It can be erased and written 1 million times, and the data storage time is 10 years. It can be erased and written automatically through programming. This is used to save recording data, and data storage does not require charging to maintain.

　　Theoretically, if the G.723 standard algorithm is used, at a sampling rate of 8kHz and a code rate of 5.3kb/s, the maximum recording time is about 100 minutes; at a code rate of 6.3kb/s, the maximum recording time is about It is 83 minutes, slightly longer than commonly used audio tapes, and can meet general recording requirements. If KM29V64000 (8M%26;#215;8=64M bit) is used, the recording time can be doubled. If longer recording time is required, a larger capacity flash memory can be selected. For detailed characteristics of KM29N3200, see reference [4].

　　 The interface circuit between KM29N32000 and ADSP-2181 is shown in Figure 4. Its read, write and erase operation instructions are as follows: (1) For read operations, first set CLE high and enter the command mode. At this time, ALE is set low, and 00H (indicating the read operation control command word) is input from the I/O port. Then CLE is set low, ALE is set high, and the address loading mode is entered. The 24-bit address (A0~A23) to be accessed is divided into three times. Enter from the I/O port from low to high. After an appropriate delay, set ALE low and read operations can be performed continuously, reading one frame of data at a time. The data obtained starts from the loading address. CE must remain low during the entire process. (2) Write operation The writing operation process is similar to the read operation. The starting control command word is 80H. After sending the load data three times, with appropriate delay, one frame of data can be continuously written to the flash memory. When the data is written, CLE is set high and the 10H command word is sent to perform the write operation. (3) When erasing operation to save data, if there is already data in the corresponding storage area, the original data must be erased first. Erase once per block of 8K bytes. First, input the control command word 60H, then send the block address in two times, and then input the D0H command word to perform block erasure. After erasing, enter the command word 70H to read the erasing status. If the LSB bit of the next read data is "0", it means the erasure is successful. If it is "1", it means an error has occurred and the erase operation can be performed again. If the error occurs again, there may be an error in the corresponding unit. In the memory operation of accessing Flash RAM, the most important thing is to pay attention to the timing of each signal. You must strictly follow the timing diagram in the instruction manual to achieve normal functions.

　　2.3 LCD display and interface circuit

　　In this system, LCD is used to display the current system status, such as recording and playback status, progress time, etc. It can be controlled by ADSP-2181 to set the display mode and content. The dot matrix LCD used is HD44780A00LCD from Hitachi. There is a special integrated circuit inside as the control driver of the dot matrix. As long as the data and instructions are directly sent, the required display can be achieved. In this system, because the LCD enable signal pulse width is large and cannot be generated directly by the DSP, the LCD enable signal is generated by triggering the monostable flip-flop 74LS123. The interface circuit is shown in Figure 5. The pulse width tW of the output Q can be controlled by adjusting the R and C values ​​connected to the 74LS123. When C≥1000pF: tW=K%26;#183;R%26;#183;C where K is a constant, related to the external temperature and external capacitance C, and can be selected between 0.2 and 0.6. When C≤1000pF, the estimated value of tW is as follows: tW=6+0.05C(pF)+0.45R(kΩ)C+11.6R When a falling pulse appears on pin A of 74LS123, the output Q generates a high level pulse, The pulse width is determined by R and C and drives the LCD to work. During recording, the upper line of the LCD displays RECORD, and the lower line displays the ongoing time; during playback, the upper line displays PLAY, and the lower line also displays the ongoing time. The time is displayed through the timer interrupt in ADSP-2181.

　　3 System control software design

　　The ADSP21XX series provides a complete set of software development tools and corresponding emulator development platforms, which provides great convenience for system debugging and simulation. Software development systems include system builders, C compilers with runtime libraries, assemblers, linkers, PROM dividers, etc. By compiling and connecting the assembly source program, an EXE file can be generated. This file is a storage image file that can be loaded into the emulator for simulation; after successful debugging, the EPROM can be written to the EPROM through the PROM divider and EPROM burning device. When the system is reset, the DSP loads the EPROM program and runs it automatically to control the entire system. Work. The system software design adopts two methods: bootstrapping and interrupt control. As soon as the boot mode system is powered on, the ADSP-2181 reads the program in the EPROM and automatically runs the program to control the entire system.

　　Interrupt control utilizes two interrupts of ADSP-2181, namely sport0 receiving interrupt and timer interrupt. The sport of ADSP-2181 is connected to AD73311. When a sampled data is obtained, a receiving interrupt is generated, and the ADSP-2181 reads and obtains the sampled data. Since sport0 is full-duplex, when a reception interrupt occurs, data can be sent at the same time. On the one hand, the playback effect can be obtained during recording; on the other hand, data can be sent directly during playback, while the sampled data is ignored, which facilitates decoding. Data is played back at a fixed bit rate. Timer interrupts the external control pin status regularly, including four pins: recording, playback, fast playback and code rate conversion. The 0/1 state of each pin corresponds to two controls, namely start recording/stop recording and start playback. There are seven states in total: sound/stop playback, 5.3kbps/6.3kbps code rate conversion and fast playback state. The structure of DSP assembly language is similar to that of ASM assembly language, and its beginning part corresponds to the interrupt vector table. When working in interrupt mode, the corresponding interrupt point in the vector table is generally a jump statement; when an interrupt occurs, it jumps to the corresponding statement to execute the interrupt control function. The interrupt setting part of the main program is as follows: JUMP start;NOP;NOP;NOP; {reset start interrupt} RTI;NOP;NOP;NOP; {IRQ2} RTI;NOP;NOP;NOP; {IRQL1} RTI;NOP;NOP; NOP; {sport0 transmit} JUMP sportReceive;NOP;NOP;NOP; {sport0 receive} RTI;NOP;NOP;NOP; {IRQE} RTI;NOP;NOP;NOP; {BDMA} RTI;NOP;NOP;NOP; { sport1 transmit} RTI;NOP;NOP;NOP; {sport1 receive} JUMP settimer;NOP;NOP;NOP; {timer interrupt} RTI;NOP;NOP;NOP; {PowerDown} sporto and timer interrupt control instructions are as follows: (1) The sporto receiving data interrupt is in the program, and the data processing is concentrated here. The main process is: during recording, every time 240 samples of data are received, G.723 encoding is performed, and the encoding results are saved in flash memory; during playback, 24 data are read each time, and the read data are Decode it, send it out through the serial port, and restore it to a voice signal through the speaker. The process is shown in Figure 6. (2) timer interrupt The timer interrupt is used to detect user control information and display running time information. There are 4 user controls, namely bit rate selection, recording control, playback control and rewind control. Corresponding to these four control pins, they are initially set to the input state, and then the working state is set by detecting the level of each pin. The process is shown in Figure 7.

　　4 System debugging

　　System debugging requires the use of a complete set of software development tools and emulators of the ADSP21XX series provided by AD. The author uses the ADSP-2181-EZ-ICE emulator for debugging. The emulator comes with a 33MHz 2181, and debugging supports 20 breakpoints. It can single-step, set breakpoints and run at full speed. The values ​​of registers and storage units can be observed and modified at any time. The emulator provides a 14-pin simulation interface through which the emulator simulates and controls the target system. There is an RS-232 interface between the emulator and the computer, which is connected to the computer's serial port through data. Software debugging can be performed on the emulator development platform. The main problems encountered during system debugging are memory reading and writing and LCD display problems. Initially it was discovered that the data written into the flash memory did not match the data read out. After careful analysis, it was found that the reason was that the flash memory was not programmed in strict accordance with the read and write operation timing, or the delay was not enough, or the order of the two signals was reversed. The data may not have been written at all, and the read data Of course it's wrong. After programming control in strict accordance with the timing sequence of its instructions, the data read, write and erase operations are completely normal. When playing recorded data, there was a problem of discontinuous sound jumps. After analysis, it was found that the cause was an error in address positioning. Because each read and write to the flash memory is one frame of data, and the data in one operation when encoding and decoding is 20/24 bytes, the lengths of the two are different, and conversion operations are required.

　　There is no information displayed when the LCD starts debugging. After analysis, it was found that the reason lies in the work cycle. The machine cycle of the ADSP-2181 processor in this system is 30ns. After setting the maximum waiting period to 7 machine cycles, it is only 240ns. The working enable pulse width of the LCD must be at least 300ns. Therefore, a monostable delay circuit was added to the hardware, which solved this problem.