Design of emulator for JTAG interface of Trimedia DSP chip

　　Trimedia integrated circuit is a high-performance DSP recently launched by Philips Company for multimedia applications. It can perform high-quality video and audio processing, and can develop various resources of Trimedia DSP and debug various applications through the online debugging tool-JTAG. In order to meet the needs of system programming in R&D and production and on-site debugging in engineering, an easy-to-use and low-cost simulator was developed.

　　1 Emulator hardware circuit composition

　　Figure 1 is the block diagram of the system. The entire emulator function can be completed by a programmable logic device. There are two interfaces in Figure 1: one is connected to the JTAG interface of the Trimedia DSP, and the other is connected to the parallel interface of the computer. The reason why the computer's enhanced parallel interface is used is that most computers now have the following ports: serial interface, parallel interface, and USB interface. The speed of the serial interface is not high and cannot meet the fast download requirements of the JTAG emulator; the data transmission rate of the ordinary parallel interface is limited to 50-150kbps and cannot meet the fast download requirements of the JTAG emulator; the USB interface is a fast computer interface , the maximum rate can reach 12Mbps, but because the interface speed is achieved when data is transmitted in block mode, it cannot meet the requirements of fast read and write conversion, so it cannot reach the data transfer rate we require. Moreover, I/O controllers with EPP and ECP functions are installed on general PCs. In EPP mode, only one IN or OUT instruction can be used to transmit 1 byte of data to the I/O controller, and then The I/O controller will process the handshake signal and generate the strobe signal. Obviously, the data transfer speed on such a machine is limited by the instruction execution rate. Data transfer rates of 1 to 1.75Mbps are usually easily obtained on contemporary machines. It can be seen that the enhanced parallel interface can meet our needs, and it is less difficult to develop the parallel interface in EPP mode. Figure 1 System block diagram Figure 2 is the emulator hardware circuit diagram.

　　TCK: Test clock, which provides a test reference clock for the TAP controller and registers. Under the synchronization of TCK, data and instructions are serially shifted in or shared through the TDI and TDO pins.

　　TMS: mode input signal. The state of TMS at the rising edge of TCK determines the working state that the TAP controller is about to enter.

　　TDI: The serial input of the instruction and data registers. The current state of the TAP controller and the specific instructions stored in the instruction register determine which register is loaded by TDI for a specific operation. At the rising edge of TCK, the data on the TDI pin is sampled and the result is sent to the JTAG register.

　　TDO: has the same operating mode as TDI, but changes state on the falling edge of TCK.

　　TAP: Test access port.

　　As can be seen from Figure 2, the design of the simulator is mainly the design of the programmable logic device CPLD, which converts 8-bit parallel data and serial data into each other. In other words, the CPLD on the JTAG side will generate TDI and TDO serial transmission and reception timings to realize mutual communication between the emulator and the Trimedia DSP chip JTAG controller. In programming, you can set the 8-bit data register for sending (TDI) and receiving (TDO), the 8-bit data register for receiving TMS, and the 4-bit (hexadecimal) counter. Both sending and receiving data are performed in bytes, and any data less than 8 bits is padded with 0s.

　　data_reg and addr_reg represent the sent 8-bit data and instruction register respectively, data_flag represents whether the data has been sent or received, data_tms_counter is the counter when sending data serially, and oscnm is the external TCK clock. NDatastb, nWrite, nAddrstb, and nReset are the parallel interface control signals of the EPP mode, data is the D0~D7 data bus of the parallel port, and tmsjtag and tdijtag are the TMS and TDI pin lines connected to the TAP controller.

　　The following is a VHDL routine for writing data and instructions to the corresponding registers: data_instruction_write:process(nDatastb,nWrite) Begin if(nDatastb"event and nDatastb="1")then if(nWrite="1")then data_reg<=data ; else data_reg<=data_reg; end if; end if; End process; tms_write:process(nAddrstb,nWrite) Begin if(nAddrstb"event and nAddrstb="1")then if(nWrite="1")then addr_reg<= data; else addr_reg<=addr_reg; end if; end if; End process; The following is the VHDL routine for sending data: (Since the receiving routine is similar to the sending routine, it is omitted.) tms_tdi_write:process(data_flag,oscnm_true) Begin if (oscnm_true"event and oscnm_true="1")then if(nreset="1")then tmsjtag<="; end if; if(data_flag="1")then if(data_tms_counter="0001")then tmsjtag<= addr_reg(0); tdijtag.