Design of non-volatile data storage based on DSP and X5165 chip

Digital signal processors (DSP) are increasingly being used, and the non-volatile storage of important data is often an indispensable part of DSP applications. Currently, non-volatile data storage methods mostly use EEPROM (Electrically Erasable Programmable Read-Only Memory) chips. The X5165 chip introduced in this article can better solve the problem of non-volatile data storage.

In a certain type of AC servo system, it is required to be able to save various parameter settings in a non-volatile manner at any time. Considering the advantages of chips with serial peripheral interface (SPI) such as simple use and small PCB board area, the 16kbit SPI EEPROM chip produced by XICOR is used to store important data.

1 Introduction to the serial peripheral interface of TMS320LF2407A
TMS320LF2407A is a 16-bit fixed-point DSP developed and produced by TI. TMS320LF2407A is manufactured using CMOS technology, with an operating frequency of 40MHz and an instruction cycle of 25ns. It integrates rich resources on the chip, supports online programming, is very convenient for development and design, and is low-priced, having entered the field occupied by traditional single-chip microcomputers.

The TMS320LF2407A device has on-chip resources including a 4-pin serial peripheral module. SPI is a high-speed, synchronous serial I/O port that allows programmable length bits to be moved in or out. Typically, SPI is used for communication between DSP processors and other chips. It allows connection to various types of chips with SPI interfaces. SPI master/slave operation also supports multi-processor communication.

The SPI interface of TMS320LF2407A has the following features:
(1) 4 external pins: SPISOMI (SPI slave output/active input pin), SPISIMO (SPI slave input/active output pin), SPISTE (SPI slave transmit enable pin), SPICLK (SPI serial clock pin). ?
(2) Send and receive operations can be completed through interrupt or query methods.
(3) Programmable baud rate, when the frequency is 40MHz, the baud rate can reach 10Mbps.
(4) Data word length: 1 to 16 data bits. ?
(5) 4 clock schemes (controlled by clock polarity and clock phase), as shown in Figure 1. The four different clock modes are as follows:

· Falling edge without delay: The serial peripheral interface sends data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal;
· Falling edge with delay: The serial peripheral interface sends data half a cycle before the falling edge of the SPICLK signal and receives data on
the falling edge of the SPICLK signal; · Rising edge without delay: The serial peripheral interface sends data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal;
· Rising edge with delay: The serial peripheral interface sends data half a cycle before the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. ?
(6) Simultaneous receiving and sending operations.

[page]
2 Hardware connection circuit?
The main features of X5165 are as follows: (1) Programmable watchdog timer; (2) Working voltage management and reset signal generation; (3) SPI interface with a baud rate of up to 2Mbps; (4) Data block locking function and on-chip accidental write protection function, etc.

TMS320LF2407A can be connected to multiple different types of chips with SPI interface. This article gives the hardware connection between this chip and X5165, as shown in Figure 2. Data is sent through the SPISIMO pin, data is received through the SPISOMI pin, and the SPICLK pin sends the clock signal. The two IO pins IOPB4 and IOPB5 are used for control (write protection) and chip select signals. ?

3 Working Principle of X5165
X5165 contains an 8-bit instruction register. The data input on the SI pin is latched on the rising edge of SCK, and the data in the chip is output to the SO pin on the falling edge of SCK. All instructions, addresses and data are transmitted with the highest bit first. The instructions and data are 8 bits, and the address is 16 bits. The clock SCK allows the operation to stop and resume afterwards. As shown in Figure 1, the clock mode of "rising edge without delay" should be selected, and the data word length is 8 bits. The instruction set of X5165 is shown in Table 1.

X5165 includes an 8-bit status register, the format of which is shown in Table 2.

In Table 2, the WIP bit indicates whether the non-volatile write operation is busy. It is a read-only bit. When it is 1, the write operation is in progress. When it is 0, there is no write operation. WEL is the write enable latch status bit. It can be set by the WREN instruction and reset by the WRDI instruction. WPEN is combined with the pin to protect the storage array and the status register bits WPEN, BL1, BL0, WD1, and WD0. It is a non-volatile bit. The WPEN bit can be programmed using the WRSR instruction. Its combination is shown in Table 3.

BL1 and BL0 are memory block protection bits, which are non-volatile bits. Their combination can be programmed through the WRSR instruction to protect the memory array range, as shown in Table 4.

The user can only read but not write the selected protected block.
WD1 and WD0 are the watchdog timer bits, which are non-volatile bits and can be programmed using the WRSR instruction.
When reading the status register, first pull the chip select signal to a low level, then send data through the SPI interface, first send the RDSR instruction, then provide 8 SCK pulses, and the register contents can be read back into the TMS320LF2407A.

When writing the status register, referring to Table 3, it can be seen that the WEL bit must be set using the WREN instruction first. Since the circuit provided in this article can control the pin, the status register can be written by directly pulling the pin level to a high level. When writing the status register, first pull the chip select signal to a low level, then send the data, first send the WRSR instruction, and then send the 8-bit content to be written. Note that the read-only bit of the status register is not affected.

When reading the memory array, first pull the chip select signal to a low level, then send data through the SPI interface, first send the READ instruction, then send the 16-bit address, and the data in the selected memory cell is read back to the TMS320LF2407A on the falling edge of SCK. After each data is sent out, the address counter in the chip automatically adds 1, and continues to provide SCK pulses to read the data of the next memory cell. When the address counter reaches $07FFH, it automatically flips to the $0000H unit. After the data is read, pull the chip select signal to a high level. [page]

Before the write operation is performed, referring to Table 3, it can be seen that "WEL" must be set. Then, the non-protected block needs to be set to readable and writable mode. According to the connection shown in Figure 2, it can be seen that the write operation can be performed by simply pulling the pin level high. Of course, it can also be implemented by programming the WPEN bit. When writing the storage array, first pull the chip select signal to a low level, then send the data through the SPI interface, first send the WRITE instruction, then send the 16-bit address, and then send the 8-bit data. After each data is sent out, the address counter in the chip automatically increases by 1, and continues to provide SCK pulses, and the data can continue to be written to the next storage unit. When the address counter reaches $07FFH, it automatically flips to the $0000H unit. After the data is written, pull the chip select signal to a high level. It is worth noting that after each write operation is completed, the WIP bit must be queried to determine whether the write operation is completed. Otherwise, if two write operations are performed consecutively, an error may occur.

4 Software Implementation of X5165 Related Operations
The serial peripheral interface module of TMS320LF2407A can easily implement various operations on X5165, and because the DSP has very rich on-chip resources, two IO pins are used to control the signal and chip select signal.
The first is the initialization of the SPI module of TMS320LF2407A. The actual source code used in this article is as follows:

The following program is used to implement the read operation of X5165. Because TMS320LF2407A is a 16-bit machine, it reads and writes two 8-bit data at a time. The source code is as follows:

The following is the sending subroutine. The register ACC is loaded with the data to be sent, and the read data is also returned to ACC. The source code is as follows:
SEND——DATA:LDP #SPITXBUF>>7?
SACL SPITXBUF; Data to be sent?
LDP #SPISTS>>7?
S——5165: BIT SPISTS, BIT6; Check SPI——INT bit
BCND S——X5165, NTC; If SPI——INT is 0, continue to query?
LACC SPIRXBUF; Read back data and save it in ACC
RETP
Due to space limitations, other software operations of TMS320LF2407A on X5165 will not be described in detail. According to the above hardware and software design ideas, X5165 has been successfully applied to a certain model of AC servo system.