Frequency scanning signal source for commodity anti-theft monitor based on DSP and DDS

Abstract: This paper proposes a method to implement a high-precision swept frequency signal source based on digital signal processor (DSP) and direct digital signal synthesizer (DDS) technology, focusing on the basic working principle of the AD9834 DDS and the characteristics of the swept frequency signal source. Hardware structure and software process. Keywords: Electronic Article Surveillance Monitor (EAS); TMS320VC5410; AD9834; Frequency Sweep Signal Source 1 Introduction Electronic Article Surveillance (EAS), referred to as EAS, is a security check anti-theft device commonly used in supermarkets. The principle is that the transmitting circuit generates a 7.8MHz to 8.8MHz frequency sweep signal, which is emitted by a near-field antenna. When there is a tag near the antenna (the tag is a high-Q LC oscillation circuit with a resonant center frequency of 7.8MHz). , the tag emits a resonant electromagnetic wave signal, which is received by the EAS receiving antenna. After demodulation, amplification and digital processing, an alarm message is finally issued. The traditional frequency sweep signal generating circuit usually contains an LC oscillation circuit composed of varactor diodes, which passes through the cycle The bias voltage of the diode is permanently changed to change the oscillation frequency. Due to the poor consistency of discrete component parameters, the oscillation frequency is difficult to accurately control. Many indicators such as the linearity of frequency change and sweep width are also strictly constrained by component performance. In the rapid development of digital technology In today's development, direct digital frequency synthesis (DDS) technology is used to generate the required signal waveforms, which is the development trend of EAS frequency sweep signal generation circuits. The author uses the AD9834 type DDS of AD Company to realize frequency sweep signal synthesis. At the same time, considering the signal The high-speed frequency change characteristics require a digital signal processor (DSP) to control the AD9834. The author uses TI's TMS320VC5410 digital signal processor (hereinafter referred to as C5410). The characteristics of these devices and circuit implementation methods are introduced below. 2 TMS320VC5410 Introduction to AD9834 This design requires C5410 to send commands and data to AD9834 through a multi-channel buffered serial port, and AD9834 generates the sweep signal required by the EAS system. C5410 is a new generation of low-power TMS320C5000 series fixed-point digital signal processor produced by TI. , it has 3 high-speed, full-duplex, multi-channel buffered serial ports (McBSP), each serial port can support 128 channels, and the speed can reach 100Mb/s. The McBSP provided by this series supports a variety of serial communications The method and protocol can be configured according to the different needs of the user. The multi-channel buffered serial port follows the SPI protocol and works in a master-slave mode. This mode usually has 1 master device and 1 or more slave devices. The interface includes the following 4 signals: serial data input (also known as master-in slave-out or MISO); serial data output (also known as master-out slave-in or MOSI); serial shift clock (also known as SCK) ; Slave enable signal (also called SS). McBSP's clock stop mode is compatible with the SPI protocol. When McBSP is in clock stop mode, the transmitter and receiver are internally synchronized. The schematic block diagram of AD9834 is shown in Figure 1. The DDS technology it uses is a technology that uses the principle of linear increase in phase of sinusoidal signals to directly synthesize the required frequency by digital accumulation and digital/analog conversion. AD9834 mainly consists of a numerically controlled oscillator (NCO), a phase modulator, and a sine lookup table ROM and a 10-bit D/A converter. The numerically controlled oscillator and phase modulator are mainly composed of 2 frequency selection registers, 1 phase accumulator, 2 phase offset registers and 1 phase offset adder. The maximum operating frequency can reach 50MHz. The frequency control word of AD9834 is obtained from equation (1) . In the equation, 0<Δphase<228-1, fMCLK can reach up to 50MHz. It is obtained from a high-stability crystal oscillator or provided by other device programming to synchronize the entire Various components of a synthesizer. The phase control word is obtained from equation (2): ΔP=Kx2π/4096 (2) where, 04 Hardware Design Plan and Software Implementation 4.1 Hardware Design Plan The hardware connection plan based on the above design ideas is shown in Figure 3, including C5410, 10MHz crystal oscillator, AD9834 and filter amplifier circuit. Since the power supply voltage of AD9834 is selectable in the range of 2.3V to 5.5V, the power supply voltage of C5410 is 3.3V. So no level conversion is required when connecting. A 10MHz crystal oscillator provides the input clock to the C5410. Initialize the C5410 to operate at 100MHz because only then can its timer period register output a 50MHz clock signal from the TOUT pin. The clock signal is output to the MCLK pin of the AD9834 as the working clock of the AD9834. Theoretical analysis points out that the phase noise of the output signal depends on the phase noise of the clock signal. When the frequency of the output signal remains unchanged, the higher the frequency of the input clock signal, the smaller the deterioration of the phase noise. The filter amplifier circuit further filters and amplifies the frequency sweep wave signal output by the AD9834 to filter out high-frequency signal interference and noise and control the signal-to-noise ratio within the allowable range. Due to clutter signal interference, the frequency sweep signal from the AD9834 contains rich high-frequency components without filtering. After processing with an RC or LC passive filter circuit, a set of frequency sweeps with a center frequency of 8.2MHz can be obtained. A relatively clear frequency sweep wave in the range of 7.7MHz to 8.7MHz. The specific implementation plan is to first filter out the frequency sweep signal output by DDS through an RC loop composed of a decoupling capacitor and a resistor. High-frequency components, and then use a complex filter circuit with an inductor (LC filter circuit can be selected). After filtering by the inductor, not only the pulsations of the load current and voltage are reduced, but the waveform also becomes smooth. The specific values ​​of L and c It can be obtained by f=1/(LC)1/2, where f=8.7MHz. The filter circuit is shown in Figure 4. Since the maximum output signal amplitude of AD9834 is only O.8V, its amplitude needs to be amplified to be used as a sweep. The frequency signal source can be realized by a high-speed operational amplifier in the system. Since this circuit is a high-speed digital and analog mixed circuit, the electromagnetic compatibility performance is very important. In particular, DSP and DDS share a power supply, so that the working signal of the device passes through the power supply. Line transmission causes interference. Usually, large-capacity electrolytic capacitors and tantalum capacitors must be installed at the power supply connection to filter out low-frequency noise. A 0.01pF to 0.1pF capacitor should also be connected to the power supply pin of each device. Coupling capacitor. 4.2 Software implementation The process of software is shown in Figure 5, which mainly includes reset, initialization, writing frequency word and control word. The initialization part includes the initialization of the DSP multi-channel buffer serial port and its configuration and alignment. When writing the control word to AD9834, the multi-channel buffered serial port operating mode and the SLEEP, RE-SET, SIGNPIB, HLB and other bits of DDS should be set. In this system design, AD9834 uses the serial control bit method to select the phase and frequency registers. ;PIN/SW=0. Select the control word mode; FSEI=0, choose to use frequency register 0 (FREQ0); D13=0, divide the 28-bit frequency register into two 14-bit registers, and the high frequency word 14 bits and the lower 14 bits can be changed independently. Since the system is required to work immediately after power-on, the RESET pin of AD9834 is connected to low level. If necessary, other modules in the system such as CPID can also be used to control DDS startup. SDATA, The three pins SCLK and FSYNC write data and control words to AD9834. When FSYNC=0, it means that a new word is being written to AD9834, and the first bit will be read at the falling edge of the next SCL.K. The remaining bits are read in on the subsequent falling edge of SCLK. After 16 falling edges of SCLK, FSYNC=1 is set to realize DSP control of AD9834. Since the McBSP of C5410 is configured in clock stop mode, the serial port reception control register SPCRl The clock stop mode bit cLKSTP and the transmit clock polarity bit CLKXP of the serial port pin control register PCR are configured as CLKSTP=11, CLKXP=1 (the clock starts on the falling edge, with delay), therefore, the transmit clock mode pin is set to Internal clock output (BCLKX=I); sample rate generator clock source comes from CPU clock (CLKSM=I); transmit frame sync mode pin is set to output (FSXM=1); transmit frame sync polarity pin is set to low power Level valid (FSXP=1); the sending clock polarity is set to falling edge sampling (CLKXP=1); the data sending and receiving delay time is l bit (RDATDLY=XDATDLY=01b); the downconversion factor of the sampling rate generator clock is 49 (CLKGDV=49). Because 16xbaud rateCLKOUT/1+CLKGDV is 100/49, the sampling rate generator of MCBSP generates a 2MHz clock signal. The following is a program segment that transmits the frequency word and control word with a frequency of 8.2MHz to the AD9834 through the McBSP port: The key point that should be paid attention to in L programming is the query of the sending and receiving ready bits. If there is no query or query in the program If the location is wrong, the program may send and receive data correctly when running in a single step, but when running at full speed, the data cannot be sent and received correctly due to the high speed. The correct query should be to query the RRDY bit or XRDY bit in SPCRl or SPCR2 before data is sent. When the RRDY bit or XRDY bit is 0, it indicates that the data has not been received or sent. Keep querying until the RRDY bit or XRDY bit is 1. Indicates that the previous set of data has been received or sent, and the next set of data can be received or sent. 5 Conclusion The frequency sweep signal source generated by DDS technology not only has stable frequency, high signal accuracy and strong anti-interference ability, but also is easy to realize intelligent processing because it is directly realized under computer control. Whether it is a practical circuit or a measuring instrument, DDS technology can in principle be used wherever a sweep signal needs to be generated. In situations where the frequency changes rapidly, the speed of register update in DDS sometimes becomes a key indicator. In this case, high-speed circuits and high-speed serial ports must be used, and reasonable hardware design and software processes must be used to achieve the expected design goals.