Design of Embedded Gateway for Distributed Jamming System Based on SOPC

Distributed jamming system is a comprehensive, integrated, miniaturized, networked and intelligent system. It is a system that installs a large number of small, light, cheap and low-power reconnaissance jammers on a small platform that is easy to deploy. It is distributed in the airspace close to the target to be jammed. It is started by command, autonomously networked, and controls the enemy's radar network, communication network, guidance network and early warning aircraft and other electronic information systems to implement close reconnaissance and jamming. This will play an important role in future electronic confrontation. The distributed jamming system adopts an approximate distributed network structure to form a "face-to-face" electronic warfare system to jointly complete the detection, positioning and jamming tasks of enemy signals. Therefore, embedded gateway is one of the key technologies in the research of distributed jamming system. At present, the research on distributed jamming system in China is still on the theoretical basis, and there is not much research on its key technologies. This paper designs a programmable system on a chip ( System on a Programmable Chip, SOPC) for distributed jamming system gateway on Field Programmable Gate Array (FPGA) for the first time , develops a simplified network application, and studies the embedded gateway technology in the distributed jamming system. Experimental results show that the SoPC designed in this paper not only meets the requirements of distributed jamming system, but also realizes high-speed transmission of control parameters and reconnaissance signal time domain and frequency domain data.

1 Requirements of Distributed Interference System for Embedded Gateway Design

According to the operational application background of the distributed jamming system, the following aspects should be considered when designing the embedded gateway hardware platform:

(1) Miniaturization. The embedded gateway should be small enough to ensure the miniaturization of the distributed jamming system.

(2) Scalability and flexibility. The distributed jamming system needs to define a unified and complete external interface to facilitate the upgrade of the software and hardware systems. Its embedded gateway should also be scalable and flexible and can be upgraded according to the needs of the combat environment.

(3) Stability and security. Stability requires that the embedded gateway can work normally within a given range of external environmental changes. Security design includes code security and communication security, which is a basic requirement for military applications.

(4) Low cost. The combat application of distributed jamming systems indicates that the systems are deployed in large quantities and cannot be recovered, so the cost of important components, including embedded gateways, must be strictly limited.

(5) Low power consumption. The hardware design of the embedded gateway directly determines its energy consumption level, and also determines the lowest energy consumption level that can be achieved through optimization of various software. Therefore, it is necessary to reasonably design the hardware system to effectively reduce the system energy consumption.

(6) Have certain signal preprocessing capabilities. The processing power of the microprocessor in the embedded system is weak, and the memory is small, and the speed of the embedded network is generally not high. This requires the embedded gateway to have certain signal preprocessing capabilities, including down -conversion and FFT transformation functions, so as to improve the efficiency of network transmission.

2 Hardware Design of Embedded Gateway in Distributed Jamming System

An embedded gateway is actually an embedded system that can realize network communication functions. With the rapid development of FPGA technology, SoPC, as a special embedded system, has the functions of software and hardware being programmable, scalable, expandable, and upgradeable in the system, and has gradually become an emerging technical direction. Therefore, this paper selects the FPGA-based SoPC solution when designing the embedded gateway of the distributed interference system, and the experimental platform selected is the ML402 development platform of Xilinx .

2.1 Hardware composition of embedded gateway in distributed jamming system

Figure 1 shows the hardware composition of the embedded gateway in the distributed jamming system. Except for the A/D, jammer and control center, these hardware are integrated on an ML402* evaluation board. The system uses an FPGA with a 32-bit MicroBlaze microprocessor soft core as the control center to process the reconnaissance signal data after A/D conversion, and then transmits the data to the control center through Ethernet, and transmits the control parameters back from the control center. DDR_SDRAM is used as an off-chip memory to make up for the small internal memory capacity of the microprocessor; the CF card stores the bit files and network configuration files of the system software and hardware; the serial port is used to control the reconnaissance receiver with remote control function , and can also output the system operation information during debugging. The functional components of the embedded gateway designed in this paper are constructed and connected in the form of IP cores inside the FPGA, which better meets the requirements of the distributed jamming system for the embedded gateway hardware design.

2.2 On-chip bus design of SoPC

Due to the limitations of the volume and power supply of the distributed interference system , its network communication must adopt burst communication, which places higher requirements on the processing power of the embedded gateway microprocessor. The bus of the MicroBlaze microprocessor is an important part of its superiority over other similar CPUs . Each bus has distinct characteristics and clear peripherals. Only by using different buses reasonably to access different peripherals and correctly coordinating the work of these buses can the advantages of MicroBlaze be maximized. Therefore, the on-chip bus design of SoPC is the focus of the system design.

Xilinx uses the IBM CoreConnect bus communication chain as the design basis for embedded processors and provides a wealth of interface resources, including the Processor Local Bus (PLB) interface, the high-speed Local Memory Bus (LMB ) interface, the Fast Simplex Link ( FSL) master-slave device interface, and the Cache Link (Xilinx Cache Link, Xilinx, XCL) interface. The PLB bus can connect peripheral IP cores to the Microblaze system and is often used in situations where speed requirements are not high; LMB is specifically used to achieve high-speed access to on-chip block RAM; and XCL is used to achieve high-speed access to off-chip memory. FSL is a FIFO-based unidirectional link unique to the Microblaze processor that can directly connect user-defined IP cores to the general registers inside the MicroBlaze, and is generally used in situations where high transmission speed requirements are required.

In the embedded gateway of the distributed jamming system designed in this paper, only parameters are transferred between SysACE CF card, interrupt control INTC, GPIO and serial port UART and MieroBlaze processor, and the speed requirement is not high. Therefore, PLB bus is used to connect with MieroBlaze processor and Multi Port Memory Controller ( MPMC ) ; MPMC and MicroBlaze processor are connected by XCL. The spectrum data of the FFT output signal of the custom IP core has high transmission speed requirements, so the FSL bus is used to directly connect with the general register inside MicroBlaze. The time domain data of the DDC output signal has the highest transmission speed requirement; to meet the transmission speed requirement, this paper develops XPS_LL_Example IP core with reference to Ethernet controller Soft TEMAC, and transmits the time domain data of the signal to MPMC for processing through the LocalLink interface of the IP core. The on-chip bus design of the embedded gateway of the distributed jamming system is shown in Figure 2.

2.3 SOPC Implementation

The SoPC designed in this paper is implemented using Xilinx's Embedded Development Kit (EDK). EDK integrates tools such as hardware platform generator, software platform generator, simulation model generator, software compiler and software debugging. Users can use EDK to arbitrarily add and reduce the hardware platform, and can easily add custom IP cores, which greatly facilitates the development process and improves design efficiency. This paper uses EDK to add IP cores of various functional components shown in Figure 2, and realizes the address allocation of IP cores and the connection of bus architecture and peripheral interfaces.

3 Software Design of Embedded Gateway in Distributed Jamming System

The software of the embedded gateway in the distributed jamming system includes an embedded operating system and a network application. EDK integrates tools such as software platform generator, software compiler, and software debugging, so software design is also carried out in EDK.

3.1 Selection of embedded operating system

The embedded operating system is the core of embedded software technology. It is between the embedded system hardware and the application program. It is responsible for scheduling and managing the application program and completing the control and operation of the embedded system hardware. The selection of embedded operating system mainly considers factors such as real-time, high reliability, low power consumption, suppressibility and compatibility, and the difficulty of software development. This paper mainly conducts technical verification of the network communication of the distributed interference system, so the relatively simple Xilkernel operating system is selected.

Xilkernel is a small, modular embedded operating system provided by Xilinx for EDK systems. Xilkernel has a complete kernel, occupies less CPU resources, and runs fast, making it an ideal operating system for small and medium-sized designs. Xilkernel itself does not have a file processing system and TCP/IP protocol stack, but it has a good interface with the LwIP library and Treck protocol stack. Together with the file system support library LibXil MFS, it can form a more complex embedded operating system.

First, select Xilkernel in the software platform settings of EDK, and select the corresponding file system and TCP/IP protocol stack. This article selects the xilfatfs file system and lwip130 protocol stack. Then configure the operating system in the operating system and library function interface, mainly setting input/output, threads and timers. Finally, execute the generated library functions and BSPs files to generate an embedded operating system environment that matches the embedded system hardware platform.

3.2 Web Application Development

The main data transmitted by the embedded gateway in the distributed jamming system is the time domain and frequency domain data of the reconnaissance signal, which directly affects the efficiency of network communication. Therefore, this paper only detects the transmission of the time domain and frequency domain data of the reconnaissance signal. The network application adopts a sequential execution structure. In order to respond to the interrupt request of the peripheral device, the program provides corresponding interrupt service routines for multiple peripheral devices. The flowchart of the network application is shown in Figure 3.

4 System Debugging

Use a gigabit network cable to connect the hardware system shown in Figure 1 to a PC, develop a network client program on the PC, and send data to control the reconnaissance receiver. Use a signal line to connect the output of the AR-ONE communication receiver to the A/D board. The A/D module uses the analog-to-digital converter (ADC) AD9460 from ADI. When the reconnaissance receiver is working under control, use a serial port line to connect the hardware system shown in Figure 1 to the serial port input of the AR-ONE communication receiver; when the reconnaissance receiver is working autonomously and the system is debugged, use a serial port line to connect the hardware system shown in Figure 1 to the PC, and observe the system operation status in the hyperterminal. Connect the signal source to the signal input of the AR-ONE communication receiver. Download the bit file generated by the joint compilation of software and hardware to the FPGA development board . The signal source outputs a 95.5MHz FM signal, and the radio monitoring and direction finding system is used on the PC for monitoring, as shown in Figures 4 and 5.

After comparison, it was found that what was displayed on the PC was the frequency domain and time domain waveform of the signal source output signal.

5 Conclusion

This paper designs a SoPC based on FPGA. The network function of this SoPC can be used to control the communication receiver from the PC, and the frequency domain and time domain waveforms of the receiver reconnaissance signal can be transmitted back to the PC in real time. At the same time, the design based on FPGA IP core makes all functional components concentrated on the FPGA chip , meeting the requirements of the distributed jamming system for volume, cost, power consumption and flexibility. If a wireless transceiver module is added , the SoPC can be used as a solution for the distributed jamming system gateway.