Design of bit synchronization clock extraction circuit based on CPLD

Asynchronous serial communication is one of the most commonly used data information transmission methods in modern electronic systems. Generally speaking, in order to correctly send and receive asynchronous serial data, it must be synchronized with the transmitted code element. The synchronous clock signal can not only be used to detect input symbols to ensure synchronization of sending and receiving, but also can provide a reference synchronization clock for the system during various processing of received digital symbols.

The bit synchronization clock extraction scheme introduced in this article has a simple principle and a fast synchronization speed. The entire system is written in VerilogHDL language and can be implemented on CPLD.

Bit synchronization clock extraction principle

This system consists of three parts: an edge capture module, a status register and a controllable counter. The schematic block diagram of the entire system is shown in Figure 1, where data_in is the serial signal input to the system, and clock is the serial signal with a frequency of A high-precision clock signal with a signal symbol rate of 2N times. pulse_out is a pulse signal generated by the system that is synchronized with each symbol bit of the input serial signal, that is, a bit synchronization clock.

The input of the edge capture module is the entire input data_in and clock. When data_in transitions, whether it is a rising edge or a falling edge, the capture module will capture the transition and generate a pulse signal clear. This clear signal reflects the moment when the input signal transitions. . Then using it as a reference, the synchronization clock of the input serial signal can be effectively extracted.

The status register has two inputs, which are connected to the output clear of the transition edge capture module and the output pulse_out of the controllable counter. When the rising edge of the clear signal arrives, the output k of this status register is set to 1, and then the pulse_out and k signals Under its own control, k is set to 0 after generating a pulse on the pulse_out and k signals. This k is generally connected to the control end of the controllable counter.

The controllable counter is a modulo-variable counter. Under the control of the k signal, the clock signal can be counted modulo N-2 or 2N. Its three inputs are respectively connected to the output clear of the transition edge capture module and the output of the status register. k and clock clock. The clear signal can clear the counter asynchronously, and the k signal can select the counting module. When k=1, the counter's module is N-2. After counting N-2, the output pulse pulse_out is generated. When k=0 , the modulus of the counter is 2N, and when the count reaches 2N, the output pulse pulse_out is generated.

When the entire system is working, when the input signal data_in transitions, the transition edge capture will capture the transition and generate a pulse signal clear. This clear signal can clear the count value of the controllable counter and at the same time The output k of the status register is set to 1 and sent to the controllable counter, so that the counter can count the module N-2. After the count is full, the pulse signal pulse_out can be output. On the one hand, this signal can be used as the output of the entire system. The bit synchronous clock signal, on the other hand, is also connected to the status register to control its output k to become 0 after the counter completes N-2 counting, and to keep K at 0 when there is no clear pulse signal. This keeps the modulus of the controllable counter at 2N until a new transition edge appears in the input signal data_in and a new clear pulse signal is generated. From the above principle, it can be seen that when the input signal is a continuous "1" or a continuous "0" , as long as the clock signal used by the system is accurate enough, it can be guaranteed to output a bit synchronization clock that meets the requirements within a certain period of time. When the input signal transitions, the system will capture this transition edge and use it as a reference to output the bit. Synchronize the clock.

Bit synchronization clock extraction

This system consists of three parts. First, the program is written in VerilogHDL language. In the second step, each part is written as a module. Finally, the three modules are connected through component instantiation to complete the entire system. System design.

The following is part of the program of the edge capture module, where Int0 is the serial input signal, PCclk is the high-precision clock signal of the input system, and the output Pcout of this module corresponds to the clear signal in Figure 1, which is also connected to the status register. Psclr of the module and clr of the controllable counter module. Its simulation structure is shown in Figure 2.

Part of the program of the edge capture module is as follows:

module PcheckCapture (PCout, Int0, PCclk);

…

reg PCtemp1, PCtemp2;

always@（posedge PCclk）begin

PCtemp1<=Int0;

PCtemp2<=PCtemp1;

end

assign PCout=PCtemp1＾PCtemp2;

…

Part of the program of the status register module is as follows. The input signal Psclr comes from the edge capture module, and the other input signal Pss comes from the output s of the controllable counter corresponding to pulse_out in Figure 1, and the output signal Psout corresponds to k in Figure 1;

module PcheckSreg (Psout, Pss, Psclr);

…

wirePstemp;

assign Pstemp=～(Pss&Psout);

always@（posedge Pstemp or posedge Psclr）begin

if (Psclr==1b1)Psout<=1;

else Psout<=～Psout;

end

…

The following is part of the program of the controllable counter module. The three input signals k, clr, and clk correspond to k, clear, and clock in Figure 1 respectively, and the output signal s corresponds to the output signal pulse_out in Figure 1;

modulePcheckCoumter(s,k,clr,clk);

…

always@（posedge clk or posedge clr）

begin

if(clr==1)begin

s=0;

cnt=0;

end

else begin

if（k==0）begin

if（cnt==2N-1）begin

cnt=0;

s=1;

end;

else begin

cnt=cnt+1;

s=0;

end

end

else begin

if(cnt==N-2)begin cnt=0;

s=1;

end

else begin

cnt=cnt+1;

s=0;

end

………

In the top-level module, three modules should be instantiated and connected by wires to form a complete system. The program of this module is as follows:

modulePcheckTop (PTout, PTint, PTclk);

inout PTout;

input PTint, PTclk;

PcheckCapture a (clear, PTint, PTclk);

PcheckCounter b (PTout, k, clear, PTclk);

PcheckSreg

c(k, PTout, clear);

endmodule

Figure 3 shows the simulation results of the entire system.

Conclusion

The local synchronous clock extraction scheme has been simulated and implemented on the CPLD device. From the above analysis, it can be seen that the local synchronous clock extraction scheme has the advantages of simple structure, saving hardware resources, and short synchronization establishment time. After a jump in the input signal, , when the system has consecutive "1"s and "0"s, or the signal is interrupted, the system can still output the bit synchronization clock pulse. After that, as long as the input signal recovers and generates a new transition edge, the system can still adjust the bit synchronization clock pulse. Output and re-synchronized. The higher the frequency of the input clock signal in this system is relative to the symbol rate, the more accurate the position of the synchronized clock will be. When the input symbol rate changes, the system can return to normal as long as the N value in this system is changed. Work.