Design of Programmable Microwave Oven Controller

Abstract: Based on the programmable logic device EPM240T100C5, the hardware description language VHDL is used, and the "top-down" design method is adopted to program a microwave oven controller chip. The design ideas and module division of the microwave oven controller are introduced, and each module and the main program are debugged separately using Quartus II software, and the hardware is downloaded to the development board for simulation debugging.
Keywords: complex programmable logic device; field programmable gate array; high-speed integrated circuit description language; Quartus II software

With the continuous development of large-scale integrated circuit technology and computer technology, the content of EDA technology is increasing at an alarming rate in the design of electronic systems in the fields of communications, national defense, aerospace, medicine, industrial automation, computer applications, instrumentation, etc.; the development of high-tech electronic projects is also increasingly dependent on the application of EDA technology. The designer's work is limited to using software to complete the description of the system hardware functions. With the help of EDA tools and the application of corresponding FPGA/CPLD devices, the final design results can be obtained. Although the target system is hardware, the entire design and modification process is as convenient and efficient as completing software design, which greatly shortens the product development cycle and greatly improves the performance-price ratio. It goes without saying that EDA technology will quickly become an extremely important component in the field of electronic design.
1 System hardware design block diagram
This system design uses the Altera MAXⅡ series EPM240T100C5 programmable logic device with high cost performance as the signal processing and system control core to complete a series of tasks including frequency division, counting, display, etc., combined with the required peripheral modules to form a minimum system to complete key control, LED display, and audio prompts. The overall design is shown in Figure 1.

The programmable features of CPLD/FPGA are used to greatly simplify the circuit. The digital system is programmed, debugged and simulated using the Quartus II software and the hardware description language VHDL, making the design and debugging convenient and giving full play to the advantages and features of CPLD/FPGA.
2 Overall design of microwave oven controller
According to the functional design requirements of the microwave oven, the software design can be composed of six modules: frequency divider, state controller, data loader, timer, display, and microwave heating signal latch. The relationship between the modules is shown in Figure 2.

2.1 Design of frequency divider fredivn
In the interface circuit, the role of clock signal is crucial. Generally, the external clock signal of CPLD can reach tens of MHz. However, due to the characteristics of some interface circuits, such high-frequency clock is not suitable for circuit operation, so a clock frequency divider circuit should be introduced to generate a working frequency suitable for the interface. The frequency divider module is designed to generate suitable scan clock, count clock and flash clock, and its external interface is shown in Figure 3. The input of the clock generator is the global clock clk, which is a signal obtained from a 50 MHz quartz crystal oscillator. The output signals are scan clocks clk 1 kHz, clk 5 Hz and clk 1 Hz.
Some key procedures are as follows:
------1 kHz frequency division---------------
process(clk)
variable count0:integer range 0 to 24999;
begin
if clk\'event and clk=\'1\' then
if count0=24999 then
clk0<=not clk0;
count0:=0;
else count0:=count0+1;
end if;
end if;
clk1kHz<=clk0;
end process;
------5 Hz frequency division--------------
process(cl k0)
variable count1:integer range 0 to 99;
begin
if clk0\'event and clk0=\'1\' then
if count1=99 then clk1<=not clk1;count1:=0;
else count1:=count1+1;
end if;
end if;
clk5 Hz<=clk1;
end process;
-----1 Hz frequency division----------------
process(clk0)
variable count2:integer range 0 to 499;
begin
if clk0′event and clk0=′1′ then
if count2=499 then clk2<=not clk2;count2:=0;
else count2:=count2+1;
end if;
end if;
clk1Hz<=clk2;
end process;
end;

2.2 Design of state controller state
Usually The state machine is the main body of the control unit, which receives external signals and state information generated by the data unit and generates control signals. The function of the microwave oven state controller state is to control the state transition during the operation of the microwave oven and send relevant control information, so it can be implemented with a state machine. By analyzing the conversion conditions and output signals during the operation of the microwave oven, its state transition diagram can be obtained as shown in Figure 4.

The state machine has 8 states. When the reset signal of the state machine is 0, the state machine is reset to the idle state. When the reset signal is 1, the state machine is in the working state or standby state. The conversion relationship of the state machine is: the current state is the idle state. When the clock rises, if the input signal test=0 or stall_1=0 or stall_2=0 or stall_3=0, it will enter the next state tap1 or tap2 or tap3 or tap4, otherwise it will remain in the idle state, realizing that the microwave oven is in the standby state when it is powered on and reset. When test=0, the state machine enters the test state tap1. When stall_1=0 or stall_2=0 or stall_3=0, the state machine enters one of the gear states tap2 or tap3 or tap4, and these three states can also be converted to each other. In each gear state, the counting state tap5 is also embedded. As long as the input time is set, if start=0, you can enter the timing state, otherwise it will remain in one of the states. When in the timing state, if stop=0, it will enter the stop state tap6, making the microwave oven stop working. The stop state tap6 and the timing state tap5 can also be converted to each other. When start=0, it will return to the timing working state, otherwise it will remain in the stop state tap6. When the timing is completed, the counter will output the done=1 signal, and it will switch from the timing working state tap5 to the end state tap7. No matter which state it is in, as long as reset is 0, the state machine will immediately switch to the initial state idle.
The external interface of the state machine state is shown in Figure 5.

2.3 Design of data loader data
The control signal of the data loading module is basically obtained from the signal output by the state machine. Its function is mainly to realize the input of time data and the output of the current state data of the microwave oven controller. When in the reset state, the data "0000 0" will be sent to the register, and the register will send the data to the data output port; in the test state, the data "8888 8" will be sent to the register, and the register will send the data to the data output port; in the end state, the data "donE 0" will be sent to the register, and the register will send the data to the data output port. When starting the gear, the gear data will also be input into the register, and then the time data can be input. The input of the time data has 4 bits - high bit min_h, low bit min_l, high bit sec_h, and low bit sec_l. Each time data input will also be sent to the register and then to the data output port. Among them, bn and sn are the outputs of the flashing enable signal. The input and output ports of the data loader are shown in Figure 6.

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2.4 Design of counter counter
According to the design requirements, counter is a down counter with a maximum timing of 99:59. Therefore, it can be composed of 3 decimal counters and 1 hexadecimal counter in cascade. The operation of the counter is related to the state of the state machine. When the state machine is in the reset state, test state, stop state, end state, and gear state, it is not working. It will only work in the counting state. If the counter enters the stop state, it will retain the current count value. When the start key is pressed again, the counter starts counting from the current value.
The count enable terminals and the set enable terminals of the four counters are connected to achieve simultaneous counting and simultaneous setting. The count pulse of the first counter is input from 1 kHz, the count pulse clk of the second counter is connected to the carry cn of the first counter, the count pulse clk of the third counter is connected to the carry cn of the second counter, and the count pulse clk of the fourth counter is connected to the carry cn of the third counter. A 4-input AND gate in the library is used in the design. All carry outputs are connected to the 4-input AND gate. When the countdown ends, done outputs a "1" signal.
2.5 Design of microwave heating signal latch latch_cook
The design of latch_cook is mainly used to latch microwave signals. The input of data is obtained by state control. When gear 1 is started, st1_en output signal is 1, st1_en output signal is 0, st1_en output signal is 0, 1_en is connected to d1, st2_en is connected to d2, st3_en is connected to d3, that is, the data of d1d2d3 input port is the output data "001" of gear 1. Similarly, when gear 2 is started, the data of d1d2d3 input port is "010", when gear 3 is started, the data of d1d2d3 input port is "011", and two processes are used in the design of latch_cook module in other states. The first process is to assign the input microwave signal to register q. When the g enable signal is 1, it is determined which gear microwave heating signal it is, and then the register q is assigned. The enable end g obtains the signal value from load_en. The output load_en is 1 signal, and there are only several working states: reset, test, end, and gear. Among them, the process can only be triggered in the gear state, and the others cannot. The second process is the latch control of the microwave signal. eo is connected to the count enable end. The process can only be triggered when counting, so that the cook outputs the signal value, otherwise the cook outputs a high impedance signal. The input and output ports of latch_cook are shown in Figure 7.

Some key procedures are as follows:
architecture one of latch_cook is
signal q:std_logic_vector(
2 downto 0); signal s:std_logic_vector(2 downto 0);
begin
s<=d1&d2&d3;
process(s)
begin
if g=\'1\'then
case s is
when"001"=>q<="001";--gear position 3
when"010"=>q<="010";--gear position 2
when"100"=>q<="100";--gear position 1
when others=>null;
end case;
end if;
end process;

process(oe)
begin
if oe=\'1\'then--output signal
cook<=q;
else
cook<="ZZZ";--high impedance
end if;
end process;
end;
2.6
Design For the display circuit, the hardware uses a serial connection design, that is, the pins corresponding to each digital tube are connected together, and the corresponding digital tube is controlled by controlling the common end (when the common end of the common cathode digital tube is high, the LED is not on; when the common end of the common anode is low, the LED is not on).
Therefore, there are 4 processes in the display module to implement the design-digital tube dynamic scanning counting process, digital tube bit dynamic scanning process, digital tube flashing display process, and decoding signal process. The display module works first by dynamic scanning counting, scanning and counting at a scanning frequency of 1 kHz. The count value obtained by scanning is passed to the digital tube bit dynamic scanning process to control the digital tube bit selection signal, that is, after displaying the first bit, the second bit is displayed, and so on, until the fifth bit is displayed, and the display module continues to display from the first bit, thereby realizing a cyclic display. Because the scanning frequency of 1 kHz makes the six digital tubes appear to be displayed at the same time, the display of the counting results and status information is realized; the decoding signal process selects the corresponding display data according to the signal value obtained by the dynamic scanning. As long as the counter data output or state changes, the display of the digital tube also changes accordingly. For the digital tube flashing display process, when ficker_seg=1, the segment signal is ANDed with the 1 Hz frequency and then sent to the output end to flash at a frequency of 1 s, one bright and one dark, all segments off, all segments on, otherwise the segment signal is output normally. The input and output ports of the display module are shown in Figure 8.

3 System debugging
In order to accurately debug the written software, the EMP240 series development board is used for system debugging. Figure 9 is a simulated operating system interface.

The main steps of system debugging are as follows:
(1) When the power is turned on and reset, the system operation interface displays: 00000. The microwave heating signal is 0. It is in standby mode.
(2) Press the TEST test key, and all the segments of the 5 digital tubes light up and flash alternately. Press the reset key, and the system returns to the reset standby state.
(3) There are three gear control keys on the right. In the standby state, just press one of the keys to set the time. The three gears can be switched between each other. Press the reset key, and the system returns to the reset standby state.
(4) After setting the time, you can press the start key to start the corresponding microwave heating signal and count down at the same time. If you want to stop heating, press the stop key, the system enters the stop state, and the microwave heating signal output is 0. If you want to heat again, press the start key again. Press the reset key, and the system returns to the reset standby state.
(5) When the timing is over, the output done is displayed, and the microwave heating signal output is 0. Press the reset key, and the system returns to the reset standby state.
This system uses EMP240T100C5 as the main control chip, and makes comprehensive use of Quartus II development tools and VHDL hardware description language, so that the hardware functions of the system design can basically be realized through software programming. After experimental simulation and debugging, the program has achieved the predetermined design indicators. This design scheme not only makes the design of electronic systems and the improvement and expansion of product performance very simple, but also replaces many original unit circuits or single-chip control chips and a large number of peripheral circuits, making electronic circuit design more flexible and convenient. In-depth exploration and practice have been carried out to realize the informatization and intelligence of microwave ovens and more household appliances.