High-precision and high-speed servo unit based on CPLD and absolute encoder

At present, the servo motors in domestic CNC machine tools are generally equipped with incremental encoders. However, the accuracy of incremental encoders is not very high and they output parallel signals. To improve their accuracy, it is necessary to increase the difficulty of encoder design and increase the output of parallel signals, which is not conducive to long-distance communication between the servo unit and the encoder. The absolute encoder, in addition to its accuracy being several times higher than that of the incremental encoder, uses high-speed serial communication for its signal input and output, saving communication lines and facilitating long-distance communication. At the other end of the encoder, CPLD is used for high-speed serial communication with the absolute encoder. The CPLD then converts the received encoder information into parallel data and transmits it to the DSP in the servo unit for calculation and control. This article will give the software and hardware design scheme for high-speed serial communication between CPLD and absolute encoder.

Hardware Design

The hardware mainly consists of three modules: power supply, CPLD and its peripheral circuits, and absolute encoder interface circuit.

Power Module

The power module consists of a switching power supply circuit and a DC/DC power supply chip, as shown in Figure 1.

The switching power supply in the figure converts the 220V AC grid voltage into +5V, +15V, and -15V. The switching power supply can filter out various interferences in the grid, and the transformer in the switching power supply isolates the 220V AC from the output +5V, +15V, and -15V. The internal circuit also uses TL431 to adjust the conduction pulse width of the switch tube. Therefore, the switching power supply has good anti-interference, safety, stability, and voltage regulation. TPS7333 is a DC/DC chip, which converts the +5V DC voltage into a stable +3.3V DC voltage for CPLD use. TPS7333 has good conversion efficiency, reliability, and voltage stability. It can convert +3.3V within the voltage range of +3.77V-+10V, so that the CPLD will not be burned out due to excessive input voltage.

CPLD and its peripheral circuit modules

The CPLD and its peripheral circuit modules are mainly composed of CPLD, CPLD programming download interface circuit (JTAG interface), DSP interface circuit, active crystal oscillator, level conversion circuit and ADM485 and its peripheral circuit (interface circuit responsible for communicating with the encoder) (Figure 2).

The CPLD in this design uses Altera's EPM570T144C5 , which belongs to Altera's MAX II. Compared with MAX I, MAX II has lower cost and lower power consumption, and the number of macro units of the device is more, and the device delay is controlled within 6ns, which has a high cost performance. EPM570T144C5 has 570 macro units, the number of chip pins is 144, of which there are 116 available I/O ports, so the resources of this chip are sufficient. CPLD is mainly responsible for high-speed serial communication with the absolute encoder, and is controlled by the DSP command to transfer the received encoder data and other information to the DSP in parallel.

The JTAG interface is mainly used to download executable files to CPLD. Install Altera's development environment - QUARTUS II on the PC, and compile the written VHDL program in this development environment. After ensuring that there are no compilation errors and that the functions have been implemented, connect the download cable to the JTAG interface and download the CPLD circuit board through the programming download tool provided by QUARTUS II.

The DSP interface is composed of 8 data lines, 3 address lines and 1 control line. The 8 data lines are responsible for transferring encoder data and other information, and the 3 address lines are responsible for transmitting DSP commands, which are decoded at the CPLD terminal. The CPLD transmits the encoder data or other information to the DSP through the 8 data lines according to the decoded commands. The control line is mainly used to complete the synchronous control of the CPLD and DSP.

The 20M active crystal oscillator mainly provides a reference clock for the CPLD. Driven by the clock signal, the CPLD generates a baud rate of 2.5Mb/s to communicate with the encoder, and generates a 10M Hz clock for some logic control signals. This crystal oscillator provides a clock frequency of 20M Hz and requires a 3.3V DC voltage from the power supply.

The level conversion circuit is mainly responsible for converting 3.3V voltage into 5V or 5V voltage into 3.3V, because the power supply voltage required by the core and I/O port of CPLD is 3.3V, and the power supply voltage and I/O port drive circuit required by ADM485 and absolute encoder are 5V, so the level conversion chip LVC4245A is needed to convert 3.3V into 5V voltage or 5V into 3.3V.

ADM485 and its peripheral circuits are the hardware connection for high-speed communication between CPLD and absolute encoder. The operating voltage of ADM485 is 5V, and its maximum communication rate is 5Mb/s. Using two ADM485 chips for docking communication can improve the anti-interference ability of the communication line, and the longest transmission distance can reach 1.2km. Its peripheral circuit is shown in Figure 3. The right half of the dotted line belongs to the peripheral circuit of the absolute encoder. The pull-up and pull-down resistors are both 1K ohms, and the current limiting resistor is 220 ohms. SDAT of ADM485 is the data output pin, SRQ of ADM485 is the data input pin, and DE of ADM485 is the external control pin, which is controlled by CPLD. Since the RS-485 communication protocol is half-duplex, ADM485 can only be in the state of sending or receiving data. When DE of ADM485 is high, ADM485 is in the data output state (that is, CPLD receives data), and when DE of ADM485 is low, ADM485 is in the data input state (that is, CPLD sends data).

Absolute encoder interface module

The absolute encoder interface module refers to the power supply and signal input and output interface circuit inside the absolute encoder. Its circuit is consistent with the above-mentioned ADM485 and its peripheral circuits. It also uses the ADM485 chip and some pull-up, pull-down and current-limiting resistors. As shown in Figure 3, the left half of the dotted line is the internal interface circuit of the absolute encoder, which is responsible for connecting with the external ADM485 (the right half of the dotted line). The ADM485 is controlled by the control chip inside the encoder. When the encoder receives the command from the CPLD, the control chip makes a judgment and sends the corresponding data, and controls the DE of the ADM485 to be high. Even if the ADM485 is in the sending state, after sending the data, the control chip makes the DE of the ADM485 in a low state, so that it can receive the command from the CPLD at any time.

Software Design

The software refers to the VHDL program of CPLD, which mainly consists of six software sub-modules: frequency divider, receiving DSP control commands, CPLD logic control, baud rate generator, receiving and sending data, and serial-to-parallel conversion and sending data (Figure 4).

• Frequency Divider Module

The divider module mainly divides the 20MHz input clock frequency into 10MHz and 2.5MHz clock frequencies, of which the 10MHz clock is mainly used to supply the CPLD logic control module, and the 2.5MHz clock is mainly used to supply the baud rate generator module.

• Receive DSP control command module

The DSP control command receiving module actually collects the control signal sent by the DSP in real time and decodes the control signal in time. After the decoding is completed, it is immediately transferred to the CPLD logic control module.

• CPLD logic control module

The CPLD logic control module is the core of the entire CPLD software. After receiving the decoded data, it immediately performs logic control operations and quickly controls the receiving and sending data modules and the serial conversion and sending data modules.

• Baud Rate Generator Module

The baud rate generator module mainly provides 2.5Mb/s baud rate for the receiving and sending data modules.

• Module for receiving and sending data

The receiving and sending data module is an important part of the entire CPLD software. It is mainly responsible for high-speed communication with the absolute encoder. Since its communication method is asynchronous serial communication, its baud rate, communication data format and RS-485 communication protocol must be the same as those of the absolute encoder.

• Serial-to-parallel conversion and data transmission module

The serial-to-parallel conversion and data transmission module mainly converts the received encoder serial data into parallel data and locks the data in the CPLD latch. When the CPLD logic control module controls it to send data, the data locked in the CPLD latch is broadcast to the DSP in parallel for DSP to perform calculation control.

Conclusion

This design has completed the entire hardware and software design. It only takes 31μs to read any position data of the motor rotor with an absolute encoder, and the communication rate can reach 2.5Mb/s. By integrating this design into the servo drive unit, the motor speed can be driven and controlled to reach 6000 rpm, and the position accuracy of the motor rotor can be controlled to reach μM level.