Embedded Multi-channel Video-on-Demand System Based on NiosⅡ Soft-core

VOD (video on demand) technology provides people with an interactive way to obtain information, and its application scope and influence are constantly expanding as the technology improves.

Traditional VOD systems mainly use servers as video information sources and provide on-demand video through local area networks, which are suitable for serving residential areas or public institutions. However, for environments with a lack of network support and high mobility, such as public transportation, traditional VOD systems are obviously difficult to implement.

Aiming at the specific user environment, this paper proposes a solution using Altera's SOPC (System on Programmable Chip), taking advantage of the flexible configuration, rich IP resources, convenient hardware design and software programming of NiosⅡ soft-core processor and FPGA (Field Programmable Gate Array), and implementing the design of a multi-channel VOD system by extending the IDE (Integrated Development Environment) interface and using the hard disk as the storage medium. The system is small in size and relatively low in cost, reflecting the advantages of embedded electronic products. Compared with traditional VOD systems, it has a more targeted scope of use, more flexible assembly, and more convenient upgrade and expansion, and has a very broad prospect.

1 System Function Division

The system can be functionally divided into four parts: system control core, multi-channel video data reading unit, video decoding module and user on-demand terminal.

1.1 System Control Core

The system uses NiosⅡ soft core as the control core, which is mainly responsible for hard disk initialization, extracting video program cluster chain, generating program list, human-computer interaction control and other tasks. After power-on, the NiosⅡ controller first initializes the hard disk transmission mode and read-write status, then reads the master boot record, addresses the operating system boot record area of ​​the basic partition, calculates the reserved sector and FAT (file allocation table) size, and obtains the entry of FAT and root directory respectively. After analyzing the files on the directory tree, extract the file name and the first cluster of the video file, search FAT again according to the first cluster pointer, trace the cluster chain of the file, and finally burn it into the Flash memory. After completing the above work, initialize the interrupt, poll the user end, wait for user requests, analyze the user instruction packet, and make corresponding responses.

1.2 Reading multi-channel video data

In order to achieve access to massive video data, the system needs an external hard disk as a storage medium. The reading and writing of hard disk data is achieved through a user-defined hard disk DMA (direct memory access) control module. Its functions include providing an interface for controlling the hard disk and multi-channel data output for the upper-level program, and generating hard disk DMA operation state machine signals. After the data is read from the hard disk, it is alternately stored in two SRAMs in a ping-pong operation. The data in the memory is arranged in parallel according to the corresponding output port. At the same time, according to the on-demand requirements put forward by the user terminal, the data is fanned out to the on-demand port.

1.3 Video Decoding

This system uses an external video decoder board as a hard decoding module. The decoding chip is LSI LOGIC's CL680 video CDMPEG 1 audio/video decoder. This chip is based on the CL480/484 architecture, used for MPEG-1 audio/video decoding, integrating digital NTSC/PAL encoding functions and enhancing KTV functions.

1.4 User on-demand terminal

To solve the problem of long-distance communication between multiple user terminals, the system uses RS-485 transceiver as the connection bridge between the host and the user on-demand terminal. RS-485 transceiver uses balanced transmission and differential reception, has the ability to suppress common-mode interference, and with the high sensitivity of the receiver, can detect voltages as low as 200 mV, greatly improving the reliability of signal transmission.

The communication method between the host and the terminal adopts a communication protocol similar to the token bus. The host continuously sends out query packets, and the client that receives the query packet is given the authority to send control commands. The client can choose to send commands or directly discard the query packet, thus avoiding the situation where multiple clients send data to the bus at the same time, resulting in communication failure.

The system uses MB90092 video character overlay module to overlay function menus on the user terminal screen, creating a friendly user operation interface. Users can perform on-demand operations through the control panel.

2 System Design

2.1 System Hardware Structure

The system hardware structure is shown in Figure 1.

To achieve the control of the hard disk and the ping-pong control of the two memories, the system uses a customized DMA control module, which is attached to the Avalon bus in the form of user logic through SOPC Builder software.

2.1.1 DMA Control Module

The block diagram of the DMA control module is shown in Figure 2.

The main function of the DMA control module is to control the hard disk to perform concurrent transmission of multiple video data. In order to ensure the quality of the video, it is necessary to consider the improvement of data reading and writing speed. This system uses a DMA module written in accordance with the ATA/ATAPI-6 protocol to control the hard disk to transmit data in Ultra-DMA mode, which can achieve a maximum transmission rate of 66 Mbit/s, meeting the concurrent transmission of multiple MPEG-1 video streams. In addition to solving the transmission rate problem, the system involves processing the reading and writing of multiple data at the same time, so the corresponding functional sub-module is introduced to control the reading and writing of two SRAMs in a ping-pong operation mode, and to manage the addresses of the storage partitions of multiple data.

The main submodules of the module are DMA controller, DMA state machine, switch and SRAM controller.

The DMA controller serves as the interface between the Avalon bus and the hard disk. Its main function is to receive control commands from the upper-level program, read and write the control registers of the hard disk, and set the hard disk's transfer mode to Ultra-DMA mode for data transmission under the control of the NiosⅡ program.

The DMA state machine module is a finite state machine implemented in Verilog HDL (hardware description language) based on the ATA (ATA/ATAPI-6) document released by the T13 group as the design standard. After the transmission mode is changed to Ultra-DMA mode under the control terminal setting, the hard disk sends a DMA request to the controller, and the DMA state machine starts. The host sends a response signal to the hard disk, and if it succeeds, the DMA STOP state is released, and IDE_HDMARDY is valid to indicate that the host is ready. Then, the data stream flows out from the hard disk and sends a double-edge latch signal. Under the control of this signal, the SRAM controller latches the data into the memory. Until the DMA request ends, the STOP signal takes effect and the DMA transmission ends. The entire process complies with the ATAPI-6 protocol, and the timing of the hard disk DMA transmission process is described using Verilog HDL.

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The Switch and SRAM controller modules are mainly responsible for scheduling data between the two SRAMs during DMA transmission, thereby realizing data ping-pong access. The Switch module is used to complete the switching between the two RAMs and the partitioned storage of data. It works in two states: with Flag as the flag bit, when Flag is 0, it performs the operation of writing to RAM1; when Flag is 1, it performs the operation of writing to RAM2. In DMA mode, a DMA reads a sector of the hard disk and just fills up a RAM. The Switch module suspends data writing and waits for an interrupt. When the data in the other RAM is fully read out, an interrupt occurs. At this time, the Switch module exchanges the read and write port addresses of the two memories.

2.1.2 RAM partition reading and writing

Since the system needs to provide multi-channel video playback, the partitioned reading and writing of each channel of video data must be realized during the DMA transmission process. When writing to the memory, a dual clock control mechanism is adopted. To implement a 32-channel VOD system, a 512 k RAM is divided into 32 units, each unit is 16 k long, and the RAM address is defined as: wraddress2 = wraddress1 + wraddress

Wraddressl is the base address of each memory partition, and its values ​​are 0 k, 16 k, 32 k, 48 k, ..., 496 k, and there is an offset address wraddress. The memory partition method is shown in Figure 3.

Define clock C0 as the write memory partition clock, C1 as the write memory offset clock, and the frequency of C0 is 32 times that of C1. When the offset address is a certain value, the value of the weight address will be traversed from 0 k to 496 k once, that is, one unit of each partition is written in each memory unit read and write cycle.

Similarly, the data in the memory must be read out in partitions and sent to the corresponding port. This module uses a memory address counting method: the length of the address line is set to 10 bits, and then the low 5 bits of the address are swapped with the high 5 bits of the address. The purpose is to start counting from the high 5 bits, and carry to the low 5 bits when the count is full. The high 5 bits represent the partition address, and the low 5 bits are the offset address of the partition. The address is accumulated from the 6th bit, just traversing 32 partitions. After the high 5 bits are accumulated in sequence, the address is carried to the low 5 bits of the partition offset address, indicating that the second memory unit of the next round of partitions has begun to be read. And so on. According to the calculated address, the data of each partition can be read in sequence. The address algorithm diagram is shown in Figure 4.

2.1.3 Shift output module

The main function of this module is to shift and output the multi-channel data read from the memory under the control of the branch clock. This module defines a set of 16-bit shift registers. The time and speed of data I/O reading and writing are determined by video_clock, which has a frequency of 12.5 MHz and is responsible for controlling the synchronization of the SRAM_R controller, the shift output module and the video decoder board. The module also sets an accumulative counter div3, which has the same working frequency as video_clock. After the SRAM_R controller reads each video file into a register in turn, it shifts out 1 bit at each falling edge of the clock until all are shifted out. If the clock frequency and buffer memory space are increased, the number of shift registers can be increased, thereby increasing the number of video output ports and increasing the number of on-demand channels of the system.

2.2 System software workflow

The system program is divided into two parts: the host program and the on-demand terminal. The host program mainly implements three functions: managing the hard disk and extracting the cluster chain; playing programs and on-demand control; responding to requests and serial port interrupts. The way to manage the hard disk is mainly to operate the control register of the hard disk through the custom DMA control module, drive the hard disk and access the corresponding sectors under the FAT32 file system, trace the cluster chain, extract the cluster chain and write it into the Flash ROM to prepare for playback. The on-demand terminal program is mainly responsible for generating instruction packets. The software workflow of this system is shown in Figure 5.

This system needs to process multiple channels of video data, and the amount of video signal data is large. During the on-demand process, the system must concentrate most of the processor time to process each channel of video signals, and the file name and cluster chain structure of the video file must be obtained through relatively low-speed PIO operations. In order to solve the bottleneck of cluster chain reading speed, this paper designs a data structure suitable for the application of this system to optimize data management and speed up reading speed. The defined data structures are:

The client status and playback progress are also recorded and managed by a dedicated structure. The defined data structures are:

3 Conclusion

SOPC = NiosⅡ soft core + FPGA, this innovative concept brings great convenience and flexibility to embedded design. Using the powerful SOPC development platform and rich IP resources, the system design cycle can be greatly shortened, and the system improvement becomes very convenient. This article proposes to integrate the user-defined hard disk read and write module into the SOPC platform and seamlessly connect it with NiosⅡ, successfully realizing the concurrent on-demand of multi-channel video data.