Implementation of Direct Digital Frequency Synthesizer with PFGA

In 1971, American scholar Joseph Tierney and three others proposed a new frequency synthesis principle based on all-digital technology, which directly synthesizes the required waveform from the concept of phase, and is called direct digital frequency synthesizer (DDS). This is a major revolution in frequency synthesis technology. Compared with the second-generation frequency synthesis technology based on phase-locked loop, DDS has the advantages of short frequency switching time, high frequency resolution, continuous phase change and flexible output waveform. Therefore, it is widely used in teaching and scientific research, communication, radar, automatic control and electronic measurement. With the continuous development and improvement of DDS technology, in recent years, its application scope has been expanded to various electronic fields such as aerospace, remote control and telemetry, instrumentation, etc.

Although there are many dedicated DDS chips on the market, the control methods are relatively fixed and therefore may not be what is needed. Field Programmable Gate Array (FPGA) devices have the advantages of fast speed, high integration and field programmability, so they are widely used in digital processing and are increasingly favored by hardware circuit design engineers. Therefore, by using these characteristics of FPGA, various relatively complex frequency modulation, phase modulation and amplitude modulation functions can be easily realized as needed.

1 DDS structure principle

DDS is a digital frequency synthesis technology that directly synthesizes the required waveform based on the concept of phase, which is mainly achieved by looking up the waveform table. According to the Nyquist sampling theorem, when the sampling frequency is greater than twice the sampled frequency, the digital signal obtained by sampling can be restored to the original signal through a low-pass filter.

The working principle of DDS is as follows: driven by the reference clock, the phase accumulator linearly accumulates the frequency control word, and the obtained phase code addresses the waveform memory to output the corresponding amplitude code. The corresponding step wave is obtained through the analog/digital converter, and finally it is smoothed by a low-pass filter to obtain a smooth and continuous waveform of the required frequency. Its structure is shown in Figure 1.

The phase accumulator is composed of an N-bit adder and an N-bit accumulator register cascaded. After each clock pulse fclk, the adder adds the frequency control word and the accumulated phase data output by the accumulator register, and sends the result of the addition to the data input terminal of the accumulator register. The data output by the phase accumulator is the phase of the synthesized signal, and the overflow frequency of the phase accumulator is the output signal frequency of the DDS. The output data of the phase accumulator is used as the phase sampling address of the waveform memory (ROM), so that the waveform sampling value (binary code) stored in the waveform memory can be found through the lookup table to complete the conversion from phase to amplitude.

The output frequency of the DDS module is a function of the system operating frequency, the number of bits N of the phase accumulator and the frequency control word. The mathematical relationship is given by equation (1).

Its frequency resolution, that is, the frequency change interval is K/2N.

2 System Functional Unit Implementation

The system design is based on the basic structure of DDS, with FPGA as the core and peripheral circuits.

2.1 Phase Accumulator

The phase accumulator is composed of an 8-bit adder and an 8-bit register in cascade. The accumulator feeds back the phase data generated by the adder after the previous clock to the input of the adder: the adder continues to add the frequency control word data under the next clock to achieve phase accumulation. When the phase accumulator accumulation result is equal to or greater than 256 (when N=8), an overflow is generated and a cycle waveform output is completed. The phase accumulator is designed and implemented in Verilog language.

2.2 Waveform Memory

The output data of the phase accumulator is used as the sampling address of the waveform memory to perform the phase-amplitude code conversion of the waveform, so that the sampling amplitude code of the output waveform can be determined at a given time. The N-bit addressing ROM is equivalent to discretizing the sine signal of 0 to 2π into a sequence of 2N sample values. If the waveform memory has D-bit data bits, the amplitude code of each sample value is stored in the analog ROM as a D-bit binary value, and the amplitude code value of the sine signal of the corresponding phase is output according to different addresses. In order to more effectively represent the waveform, of course, it is expected that the number of bits of the binary value output by the waveform memory is as large as possible. However, the design of the lookup table and the selection of the D/A converter are related, so it is necessary to select a D/A converter with a high bit number. The sine table designed in this paper has a 16b output and 256 sampling points.

2.3 Implementation of D/A conversion circuit

The D/A conversion unit is the unit that converts the waveform amplitude in digital form into an analog signal of the required synthetic frequency after the waveform data generation unit. The DAC output signal is actually a step analog signal, and the waveform needs to be smoothed using a low-pass filter after D/A conversion. Here, the A/D converter MAX5885 chip produced by Maxim is used. The chip needs to convert the input clock signal into a differential input, and the external chip MAX6161 provides a 1.2V reference voltage. The differential output after D/A conversion can be converted by a transformer to obtain the required signal:

3 System Software Design

3.1 Design of the Accumulation Control Module

The phase accumulator mainly completes phase accumulation and realizes the function of adjustable output waveform frequency. This module is implemented in Verilog HDL language. If the DDS system requires high precision, the number of bits N of the phase accumulator needs to be larger. Here N=8, and its Verilog HDL key code is as follows:

The data signal is an 8-bit frequency control word. By changing the value of data, the output of waveforms with different frequencies can be achieved.

3.2 Design of waveform memory

Different programmable devices use different methods to design ROM lookup tables. They are mainly based on the IP core Single Port Block Memory and Verilog selection statements. To use the waveform storage table of Single Port Block Memory, you only need to generate a data file *.mif or *.coe, and then directly add the data file when customizing Single Port Block Memory. However, this method can only be used when the FPGA supports internal embedded array blocks (EAB); using Verilog selection statements is more intuitive, but this method is more cumbersome when the input data volume is large. This design uses the first method.

The coe file is a file used as memory (ROM or RAM) initialization input during compilation and simulation, namely, memory initialization file. There are many ways to create a coe file. In this design, C language is used in Matlab to generate a coe file. The format of coe file writing is as follows:

Change the suffix of the generated cos.txt file to .coe, open the file and change the comma in the last line to a semicolon, and add the following two lines at the beginning of the file:

Finally, save the file and exit, and load it into the ROM generated by Single Port BlockMemory. When loading, pay special attention to the parameter settings of data base and data length.

4 System Functional Simulation and Verification Analysis

The accumulator controller and ROM lookup table form a whole to realize a basic DDS system. This design uses the atomic clock (33MHz) as the reference frequency input, takes the accumulator as 32 bits, and realizes an output frequency of 700kHz.

Usually the number of bits N of the phase accumulator is very large, and the actual design is limited by the size and cost. In order to save the capacity of ROM, the phase truncation method is adopted, and generally only the upper bits of the accumulator output are used as the ROM address. In the design, the upper 8 bits (N=8) of the accumulation result are taken for table lookup, that is, the cosine ROM has 256 addressing addresses and the data width is 16.

5 Conclusion

Direct digital frequency synthesis (DDS) technology belongs to the third generation of frequency synthesis technology. Compared with the second generation frequency synthesis technology based on phase-locked loop, the output waveform synthesized by DDS technology has good performance indicators. The design uses the XC3S200 chip of Xilinx's Spartan-3 series and the high-speed 16-bit D/A converter MAX5885. Based on the working principle of DDS, the design method of DDS based on FPGA is introduced. The output frequency and resolution can be flexibly controlled by setting parameters. The design has high precision, selects parameters to control the output signal, and produces an ideal waveform. From the test results, it can be seen that the system works stably and reliably, and has good reference and practical value.