The Small Chip Alliance is established, are mainland chips in danger?

On March 3, global leading chip manufacturing companies Intel, AMD, ARM, Google Cloud, Meta (Facebook), Microsoft, Qualcomm, Samsung, TSMC, etc. jointly announced the establishment of the Small Chip Alliance and the launch of a new universal chip interconnect Standard: Universal Chiplet Quick Connect (UCle).

This standard is designed for chiplets and aims to develop a new open standard for chiplet interconnection, simplify related processes, and improve interoperability between chiplets from different manufacturers.

Under this standard, chipmakers can mix and match chips where appropriate.

Small chips are currently an important technical idea to break through the limitations of Moore's Law.

The China Computer Federation (CCF) once evaluated that "core chip (small chip) design technology will be one of the most important development results in the field of integrated circuits in the next 10 to 20 years."

The U.S. Defense Advanced Research Projects Agency (DAPRA) launched the "Common Heterogeneous Integration and IP Reuse Strategy (CHIPS)" project in August 2017, which is part of DAPRA's "Electronics Resurgence Initiative (ERI)" with a total investment of US$1.5 billion. Part of the effort is to promote a compatible, modular, and reusable small chip ecosystem.

Omdia, a well-known market research organization, predicts that the global market size of small chips will expand to US$5.8 billion in 2024, a nine-fold increase from US$645 million in 2018. By 2035, the small chip market is expected to increase to US$57 billion.

Source: Omdia

What is a chiplet?

In 1965, Gordon Moore, former president of Intel, published a Moore's Law prediction in the technical journal Electronics: When the price remains unchanged, the number of transistors that can be accommodated on an integrated circuit will increase every 12 months (later revised to 24 months) will be doubled, and the performance will be doubled.

The emergence of Moore's Law set an extremely critical benchmark for the pace of technological development, which greatly promoted the semiconductor industry that was confused in its progress at that time.

However, in recent years, as the cost of R&D and manufacturing investment has continued to increase, Moore's Law of doubling the number of transistors every 24 months has gradually become invalid. After all, at the physical level, an infinite number of transistors cannot be placed on a small chip. When the number of transistors approaches the physical limit, how to find new breakthroughs has become the most worthy of consideration for many chip manufacturers.

Currently, the vast majority of chip manufacturers are taking the SoC (System on Chip) route. Purchase soft-core IP or hard-core IP from different IP suppliers, combine it with self-developed modules to form a system on a chip (SoC), and then produce the chip with a certain manufacturing process node.

SoC is essentially an integration of chips. For example, the mobile phone processor we often talk about is actually an integration of CPU, GPU and other chips, and it is also an SoC.

The advantage of this technology is that while improving the communication speed between modules, it can also achieve low power consumption and low cost.

However, in recent years, the difficulty and cost of breaking through advanced manufacturing processes have been rising.

2001: The chip manufacturing process was 130nm, and the Pentium 3 processor was very popular at that time.

2004: The first year of 90nm.

2012: The process technology has developed to 22nm. At this time, many manufacturers such as UMC, MediaTek, and GlobalFoundries can achieve the 22nm semiconductor process technology.

2015: A watershed in the development of chip manufacturing. When entering 14nm, UMC stopped there.

2017: Entering the 10nm era, Intel stopped at 10nm. The i5 and i7 processors were delayed in delivery due to yield issues.

2018: With the advent of 7nm, Intel has been unable to break through so far, and another American chip foundry giant, GlobalFoundries, also collapsed at 7nm.

2019: 6nm begins mass production.

2020: The manufacturing process began to enter the 5nm era, entering the more difficult 5nm. Only Samsung and TSMC survived, but Samsung was revealed to have faked its yield rate.

How to break through 5nm has become the biggest R&D bottleneck for many chip manufacturers. Although Samsung has previously announced that it has achieved mass production of 5nm chips, it has also been involved in a yield fraud scandal.

The emergence of small chips shoulders the mission of "breaking through" the physical launch of chips.

Chiplets are commonly known as core chips. It is actually reuse at the silicon wafer level. It is a model of building cores using building blocks. It converts a type of die that meets specific functions through die-to-die (die to die). Chip) internal interconnection technology enables multiple module chips to be packaged with the underlying basic chip to form a system chip to achieve a new form of IP reuse.

In addition, through advanced packaging technology, small chips can integrate a variety of different architectures, different process nodes, and even dedicated silicon blocks or IP blocks from different foundries, so that they can skip tape-out and quickly customize products. A super chip product that can meet a variety of functional needs.

In a chiplet integrated module, different processor nodes can be used simultaneously, so there can be a mix of 5nm chiplets that handle high-performance tasks, and 12nm and 14nm chiplets that are more focused on less rigorous tasks.

This new design method can not only greatly simplify chip design complexity, but also effectively reduce design and production costs.

AMD released the Ryzen3000 series in 2019, which deployed Zen2 cores based on small chip technology; Intel released Ponte Vecchio, which integrates 47 small chips, all of which are typical small chips.

In recent years, as leading manufacturers have taken the lead in investing more experience in the research and development of small chips, small chip technology has gradually moved from the laboratory to practice.

Why was the Small Chip Alliance established?

There are actually two logics behind the establishment of the Small Chip Alliance. One is to be optimistic about the technical advantages of small chips themselves, and the other is to hope to clear the obstacles to the advancement of small chips through the alliance.

We mentioned earlier that one of the characteristics of small chips is the core-making mode of building blocks. This means that in the arrangement and combination of chip modules, designers can choose the most advanced technology for specific parts, and choose more advanced technologies for other parts. Mature and more economical technology to achieve spliced ​​combination modules, thereby reducing overall costs.

For example, AMD's second-generation EPYC processors and Ryzen both use small chip designs, combining more advanced CPU modules manufactured by TSMC's 7nm process with more mature I/O modules manufactured by GlobalFoundries' 12/14nm process. , so that its products can meet the needs of high computing power with 7nm, while 12/14nm reduces manufacturing costs.

The benefit of this is that the chip area of ​​the 7nm process is significantly reduced, and the use of I/O modules using more mature processes helps improve the overall yield and further reduce wafer foundry costs.

Taken together, the more CPU cores there are, the more obvious the cost advantage of a small chip combination.

Ideally, with the help of the small chip approach, chip design companies only need to focus on the IP they are good at without worrying about other IPs. This not only helps improve core innovation capabilities, but also spreads R&D costs through multiple IP designs.

On the other hand, the small chip solution has good scalability. For example, after building a basic die, you may only use one die for laptops, two for desktops, and four for servers.

In addition, small chips can act as heterogeneous processors, combining different processing elements such as GPUs, security engines, AI accelerators, and IoT controllers in any number to provide richer acceleration options for various application needs.

As the advantages of small chips are gradually revealed, they are being adopted by more advanced and highly integrated semiconductor devices such as microprocessors, SoCs, GPUs, and programmable logic devices (PLDs).

However, for small chip technology to mature, it still needs to face many challenges.

In small chip technology, the die-to-die link method is adopted, and the interconnection interface and protocol must be considered for each die interconnection.

Many complex factors such as process technology, packaging technology, system integration, and expansion must be taken into consideration in the design. At the same time, it is also necessary to meet the requirements for information transmission speed, power consumption, etc. in different fields.

This makes the design process of small chips very complicated, and the biggest difficulty facing small chips comes from the lack of a unified protocol.

Marvell (formerly Marvell Technology) launched the MoChi architecture, a small chip model, in 2015. Since then, Marvell has been stuck in the difficulty of choosing an interface. According to Marvell CTO Yaniv Kopelman, they do not want to use interposers or InFO-type packaging because they do not want to pile up packaging costs or be tied to a single supplier.

In addition, when using chiplets, IP must be divided in the middle, but where to divide and how to develop the architecture also poses challenges to the implementation of the final product.

Yaniv Kopelman concluded: “It’s easy to build IP in a demo, but there’s still a long way to go from demo to production.”

For a long time in the past, small chips have been attracting attention from the chip design industry. More and more manufacturers are starting to use chiplets, making them more and more common. Manufacturers hope that small chips can solve many problems such as manufacturing cost and scalability that chip manufacturing currently faces.