Accelerate automotive electronics design with system optimizing compilers

Thanks to Moore's Law, automotive electrical systems have experienced rapid technological growth. Modern cars have come a long way from being simple engine electrical systems coupled to an AM radio. Today's modern cars are equipped with a variety of advanced electronic systems that perform functions such as engine control, advanced driver assistance systems (ADAS), traction and stability control, infotainment, and also provide autonomous operation capabilities for some cutting-edge applications. 

This significant growth in the deployment of electronic systems within vehicles also creates several challenges that must be addressed by designers:

Performance – Real-time, low-latency, and highly deterministic performance is required to enable multiple in-vehicle functions such as ADAS, ECUs, traction and stability control, etc.

Safety – Automotive electronic systems perform critical functions and failures can result in injury or death. Therefore, the system must implement information security and anti-tampering technology to prevent unauthorized modifications.

Safety – Must comply with the automotive safety integrity level specified in ISO26262.

·Interfaces – must be able to connect to a variety of sensors, actuators and other actuators.

Power efficiency – Must operate efficiently within a limited power budget.

Software-defined – Highly flexible to adapt to different standards and conditions in multiple markets.

To address these challenges, automotive electronic system developers are deploying heterogeneous system-on-chip ( SoC ) devices. Heterogeneous devices combine a processing unit (usually multiple cores) with one or more heterogeneous co-processors (such as GPUs, DSPs, or programmable logic).

Combining processing units with programmable logic creates tightly integrated systems that take advantage of the inherent parallelism of programmable logic. This allows programmable logic (PL) to implement high-performance algorithms and interface connections, while the processing system implements higher-level decision-making, communication, and system management functions. When combined, the programmable logic can be offloaded with processing tasks, creating more responsive, deterministic, and energy-efficient solutions.

In terms of interface connectivity, heterogeneous SoCs can support a variety of industry-standard interfaces that can be implemented through the processing system or programmable logic. Thanks to the flexibility of the IO structure, key legacy and custom interfaces can be implemented using programmable logic. However, this requires the addition of an external PHY to implement the physical layer of the protocol to provide any-to-any connectivity.

Some heterogeneous SoCs provide support for multiple device-level and system-level security features for easy implementation. These devices are capable of encrypting and authenticating the boot and configuration processes. If the processor core is based on an ARM processor, Trustzone can be used to secure the software environment. With Trustzone, the development team can create an orthogonal environment to restrict software access to the underlying hardware by using a program manager. In addition, there are several additional design options, such as functional isolation, that can be implemented in the design to further strengthen the security solution depending on the requirements.

The traditional heterogeneous SoC development process divides the design into two parts: the processor system and the programmable logic. This approach used to require two independent development teams, which would increase non-repetitive engineering costs, development time and technical risks. In addition, this approach also fixes the design functions in the processor core or programmable logic, making it difficult to perform later optimization.

What is needed is a development tool that enables software-defined development of the entire device, with the ability to move functionality from the processor core to the programmable logic as needed, even by non-HDL experts.

This is where system optimizing compilers come in. System optimizing compilers enable the entire system behavior to be defined in software using high-level languages ​​such as C, C++, or OpenCL. The functional partitioning between the processor system and the programmable logic is then performed using a system optimizing compiler, which enables seamless movement of functionality to choose whether to run in the processor system or be implemented in the programmable logic.

Figure 1 – Using the system optimizing compiler to select functions to accelerate.

By timing the execution time of functions using built-in timers within the processing system, the functions that cause bottlenecks can be identified, thereby creating a list of bottleneck functions. These bottleneck functions then become candidates for acceleration in the programmable logic using a system optimizing compiler.

Movement between the processing system and programmable logic is achieved through a combination of high-level synthesis (a tool that converts C, C++, OpenCL programs into Verilog or VHDL descriptions) with a system-optimizing compiler and a software-defined connectivity framework. The software-defined connectivity framework seamlessly connects HLS results to software applications, allowing design teams to move functions between the processor and programmable logic with a single click. Of course, when users move functions to programmable logic, they also get a significant performance boost, which is naturally a result of using programmable logic. Acceleration in the PL also improves determinism and reduces latency compared to CPU/GPU solutions, which is critical for applications such as ECUs and ADAS.

Figure 2 – Resource and performance estimates using a system optimizing compiler.

Library support

Many automotive applications are developed using industry-standard open source libraries, such as OpenCV or Caffe in ADAS systems, or standard math libraries in ECUs. To accelerate the development of these applications, the system optimizing compiler needs to be able to support multiple HLS libraries for developers to use in their applications. The system optimizing compiler should support several key libraries, including:

OpenCV – accelerates computer vision functions

Caffe – Accelerates machine learning inference engines

Math Library – Provides a synthesizable implementation of the standard math library.

IP Library – Provides IP library for implementing FFT, FIR and shift register LUT functions.

Linear Algebra Library – Provides a library of general linear algebra functions.

Arbitrary Precision Data Type Library – Supports arbitrary length data that is not a power of 2 using signed and unsigned integers. This library allows developers to use FPGA resources more efficiently.

The provision of these libraries provides considerable support to development teams, freeing them from having to develop similar functionality.

Real Examples

A key element of many automotive applications is the protection of data from unauthorized modifications that could result in unsafe operations. A common algorithm used to secure stored and transmitted data is the Advanced Encryption Standard (AES). AES is an example of an algorithm that is described at a high level but is best implemented in a programmable logic architecture. To demonstrate the benefits of using a system optimizing compiler, a simple AES 256 application has been developed targeting three common operating systems. This example was initially executed only in the processor system, and then the function was accelerated in the programmable logic. 

Figure 3 - AES acceleration results on different operating systems when using a system optimizing compiler.

in conclusion

Heterogeneous SoCs address the challenges faced by automotive electronic system designers. Using high-level languages, system-optimizing compilers enable the development of these devices, and once the application functions are developed and prototyped using the processor, the functional partitioning between the processor system and programmable logic can be optimized, thereby reducing development time and achieving safer, more responsive, and more energy-efficient solutions.