Design and implementation of ECG signal processing system based on ARM

This paper designs an ECG signal processing system with digital and information characteristics. The system uses a 32-bit high-speed ARM processor as the hardware platform and a real-time operating system as the software platform. It schedules and allocates the resources of the hardware system, achieves the effect of real-time processing of ECG signals, and realizes functions such as real-time display and real-time storage of ECG signals.

According to statistics, there are 13,000 hospitals at or above the county level in my country, with a total of 175,000 medical machines. Together with some professional heart disease treatment institutions, the number of outpatient visits for heart diseases in my country is about 10 million per year. According to the goal of the National Health Informatization Development Plan of the Ministry of Health, the digitization and informatization of hospitals should be basically realized in 2010. Therefore, the future medical device market has huge market space for new medical equipment, especially the ECG signal processing system with digital and informatization features, which has broad application prospects and practical value. This article introduces the design of an ECG signal processing system based on ARM.

Overall system design

The main function of the system introduced in this article is to process and transmit ECG signals in real time. The system principle block diagram is shown in Figure 1.

Figure 1 System block diagram

The ECG signal is extracted through the electrode and enters the analog processing module. After amplification and filtering in the analog processing part, the signal strength and signal-to-noise ratio are improved. The signal is quantified and converted into a digital signal and enters the digital processing module. In the digital processing module with the ARM processor as the core, the ECG signal is stored in a buffer. After being scheduled by the real-time operating system, it is transmitted to the PC through the USB channel. The software module of the PC includes the reception of USB channel data and the processing of ECG signals. The processed ECG signal further improves the signal-to-noise ratio and is displayed on the screen, thereby helping doctors diagnose heart diseases.

1 S3C44B0X processor

The S3C44B0X microprocessor is a high-performance and cost-effective microcontroller solution provided by Samsung for portable devices. It uses the 32-bit low-power RISC core ARM7TDMI, is manufactured using 0.25μm CMOS technology, and supports the new bus structure SAMBAII (Samsung ARM CPU embedded Microcontroller Bus Architecture). At the same time, based on the ARM7TDMI core, the S3C44B0X has expanded a series of general peripheral devices to minimize the system cost and the number of peripheral devices. These functional components can be divided into CPU unit, system clock management unit, storage unit and system function interface unit.

The main functions integrated on the chip are: adding 8KB of cache based on ARM7TDMl; external expansion memory controller (FP/EDO/SDRAM control, chip select logic); LCD controller supports up to 256 colors of DSTN, and has 1 LCD dedicated DMA channel; 2 general DMA channels, 2 DMA channels with external request pins; 2 DARTs with handshake protocol: 1 SIO; 1 I2C bus controller; 5 PWM timers and 1 internal timer; watchdog timer; 71 general programmable I/O ports, 8 external interrupt sources; power consumption control modes include normal, low, sleep and stop; 8-channel 10-bit ADC; RTC (real-time clock) with calendar function; PLL clock generator.

2 Real-time operating system μC/OS-II

μC/OS-II is a complete, multi-portable, curable, and customizable preemptive real-time multitasking kernel. μC/OS-II is written in ANSI C language and contains a small amount of assembly language code, making it available for microprocessors of different architectures. So far, μC/OS-II has been running on more than 40 microprocessors of different architectures, from 8-bit to 64-bit. μC/OS-II has been used in many fields around the world.

μC/OS-II is a "real-time kernel" that makes it easy to design and expand applications, and new features can be added without major changes. By dividing the application into several independent tasks, RTOS greatly simplifies the application design process.

Hardware system design

1 UART asynchronous serial interface design

In this article, ECG data is transmitted to the PC through the USB channel, but due to the complexity of the USB interface, the asynchronous serial interface is required when debugging USB devices. In addition, when the USB driver cannot be used or installed on some old PCs, the asynchronous serial interface can be used as a backup low-speed transmission method, which also increases the scalability of the system.

Figure 2 is a connection diagram of the serial interface circuit of S3C44B0X with RS232 level conversion in the ECG signal processing system. In the figure, the RS232 level conversion chip is MAX3232, and its RxD0, TxD0 and RxD1, TxD1 are connected to the 99th, 100th and 103rd, 104th pins of S3C44B0X respectively.

Figure 2 Serial port connection diagram

2 USB device interface circuit design

Due to the complexity of USB protocol, USB device controller must be able to detect and respond to USB port events and provide data storage functions. Considering the cost performance and technical data, the PDIUSBD12 chip produced by PHILIPS that supports USB1.1 protocol was selected in this system.

Figure 3 is the hardware connection diagram of PDIUSBD 12 and S3C44B0X. In the figure, the D0~D7 pins of USBD 12 are connected to the data bus D0~D7 of S3C44B0X respectively, and A0 is connected to the address bus ADR0 of S3C44B0X. A0 is the address bit. When A0=1, the command instruction is selected; A0=0, the data is selected. J8 is the USB slave interface (slave), which can be connected to the USB port of the PC through a USB cable.

Figure 3 USB interface circuit

3 FLASH ROM circuit design

In the ECG signal processing system, S3C44B0X is the central processor of the hardware part, and the real-time operating system μC/OS-II is the scheduling center of the hardware resources. It is stored in the FLASH ROM. After each system initialization, S3C44B0X copies it to SDRAM before executing the application.

In this system, the multi-purpose FLASH memory SST39VF160 with a capacity of 1M×16bit produced by SST Company is used. The ARM and FLASH interface circuit is shown in Figure 4.

Figure 4 ARM and FLASH interface circuit

When S3C44B0X is reset, it immediately starts to fetch instructions from address 0x00000000. Therefore, the system startup code is placed at address 0x00000000, and the memory located at 0x00000000 is called BOOT ROM. In ARM systems, Flash ROM that can be quickly read and easily rewritten is usually used as BOOT ROM. The processor does not require any software settings for the Flash ROM interface. When the system is powered on for the first time, the CPU can read the Flash ROM.

4. Interface circuit design of external main memory SDRAM

In the real-time operating system μC/OS-II, each task has an independent stack, which is composed of continuous memory space. During the transmission of ECG signals, a buffer is also required to store data, including the stack required for system software operation. All of these require the system's main memory to allocate space.

The S3C44B0X has only 8KB of internal cache and no RAM for running programs and storing temporary data, so an external SDRAM must be used as off-chip main memory. In this article, the IS42S16400 with a capacity of 1Mb×16×4Bank produced by ICS is used.

The connection diagram between S3C44B0X and SDRAM is shown in Figure 5.

Figure 5 Connection diagram between S3C44B0X and SDRAM

Software system design

In order to realize the quantification of ECG signals and the processing and transmission of data, make full use of the real-time performance of μC/OS-II, and make the software system have good reusability to provide conditions for the future expansion of system functions, the software design of this system is shown in Figure 6.

Figure 6 Software system design flow chart

Anti-interference design

After the ECG signal is transmitted to the PC, it needs to be displayed on the screen to form an ECG. The 12 leads used in the ECG signal processing system are displayed as 12 ECG waveforms on the screen. Each waveform contains specific information, but in order to obtain an ECG waveform close to the ideal, the signal must be preprocessed.

From the perspective of measurement technology, ECG signals are low-frequency weak signals under a strong noise background, with an amplitude of 10μV to 5mV and a main frequency range of 0.05 to 100Hz. Therefore, in the process of detecting, extracting, amplifying and recording ECG signals, there are interferences from the human body itself, such as myoelectric interference, and interferences from the outside world, such as power frequency interference. These interferences reduce the signal-to-noise ratio of the system and may even drown out weak effective ECG signals. Therefore, signal preprocessing is required to eliminate various interferences. This paper uses an adaptive noise canceller for preprocessing, as shown in Figure 7.

Figure 7 Structure diagram of adaptive noise canceller to eliminate noise

Conclusion

Experiments show that the ECG signal processing system based on ARM designed in this paper adopts modular design of software and hardware for signal acquisition and processing, which improves the accuracy of ECG signal detection. The designed software and hardware system with ARM processor as the core and USB communication interface improves the stability and reliability of the system, reaches the expected technical indicators, and provides a theoretical basis and basis for the design of new ECG signal processing equipment. This system will also play an important role in the diagnosis of heart disease.