Full-color independent video LED system based on ARM and FPGA

At present, there are two main types of display screens according to the data transmission method: one is a real-time video screen that uses the same content as the computer; the other is an independent video source display screen that sends the display content to the display screen through communication means such as USB and Ethernet. If wireless communication is used, the display content can be updated at any time, which is highly flexible. In addition, using an embedded system to replace the computer to provide the video source can not only reduce costs, but also have high feasibility and flexibility, and is easy to construct. Therefore, the demand for independent video source LED display systems is increasing.
This system adopts the ARM+FPGA architecture, making full use of the super processing power and rich interfaces of ARM to achieve true network remote operation. Therefore, it can not only be used as a general LED display screen controller, but also can form each display node into a large outdoor advertising media network. FPGA is a very flexible programmable logic device that can be programmed to configure like software, so that flexible and convenient changes and development can be made in real time, improving system efficiency.

1 Independent video LED system
The main performance indicators of LED display screens include field scanning frequency, resolution, grayscale and brightness. Resolution refers to the number of LED tubes that the controller can control, grayscale is the resolution of color, and high brightness requires a long display time for each grayscale. Obviously, these three indicators will greatly reduce the field scanning frequency, so it is necessary to make appropriate trade-offs between these indicators in different occasions. Usually, the grayscale, brightness and field scanning frequency are determined by a single controller, while the resolution can be greatly improved by means of a controller array. In this way, the grayscale and brightness of each controller are very good, the field scanning frequency is also appropriate, and then a large control area is achieved through the form of a controller array, so that a full-color ultra-large screen LED display controller with delicate colors can be realized. The independent video LED system is completely independent of the control of the computer and can realize communication, video playback, data distribution, scanning control and other functions. In order to achieve a large screen, full color and high field frequency, this system adopts a controller array mode, as shown in Figure 1.

Figure 1 Independent video LED system structure
The system can update local data from the network server through the network interface (Ethernet interface), and the video playback part obtains the video stream in RGB format by decoding the data. Then, the data are sent to different LED display controllers through the data distribution unit, and the controller displays the data provided by the playback unit on the full-color large-screen LED.

2 Communication interface and video playback unit
The communication interface and video playback part of this system are implemented by ARM uClinux. ARM (Advanced RISC Machine) is a general-purpose 32-bit RISC microprocessor architecture designed and developed by the British ARM company. The design goal is to achieve miniaturization, low power consumption, and high-performance microprocessors. Linux, as a stable and efficient open source operating system, has been widely used in various fields, while uClinux is a Linux system designed specifically for the microcontroller field. It has the advantages of being scalable, small kernel, perfect network interface protocols and interfaces, excellent file systems, and rich open source resources. It is being adopted by more and more embedded systems. The system uses the Intel XScale series PXA255 chip, which is compatible with the ARM v5TE instruction set. It uses ARM's memory management, interrupt processing and other mechanisms, and has made some extensions on this basis, such as DMA controller, LCD controller, etc. Due to the limited processing power of ARM9, it is currently only used to play 320×240 pixel videos.
The data for system video playback comes from the SD memory card (Secure Digital Memory Card) in the system. There are two ways to update the data in the SD card: one is to use a computer to update the data in the SD card; the other is to receive data from the server through the network and update the SD card directly from ARM. In addition, the player can also directly play MPEG-4 format data transmitted by the network. Since XScale does not provide a physical layer interface, if you want to realize the network function, you need to connect an external physical layer chip. This system uses SMSC's high-performance 100M Ethernet controller LAN9118. [page]

3 Video data distribution
Since the controller adopts array mode, it is necessary to distribute the data provided by the video source and correctly send the data of different rows and columns to different controllers.
3.1 Data distribution unit solution
The grayscale of the LED controller in this system is as high as 3×12 bits (can display up to 64G colors) and the control area is 128×128 points. The data provided by the system playback unit is 320×240 pixels, so it needs to be decomposed into 6 LED controllers for control (see Figure 1). Therefore, it is necessary to send the RGB data provided by PXA255 to these 6 controllers in 3 groups, which is implemented by FPGA. The solution is shown in Figure 2.

Figure 2 Data distribution unit solution
The LCD interface submodule receives the data and control signals of the PXA255 LCD interface, corrects the input data point by point, and stores it in SDRAM, then divides the field data into 3 groups, each with 128 lines (the last group has only 64 lines, and the bus scheduler fills zeros here for the consistency of the control board later), sends them at the same time, and then processes them by the LED display controller.
3.2 Memory allocation and bus scheduling
In order to facilitate the interface between modules and facilitate data synchronization in different clock domains, the system memory adopts a two-level storage mode, that is, SDRAM is used as the main memory, and each module also has a corresponding FIFO as a cache. SDRAM has the advantages of large capacity, high bandwidth, and low price; but the control is relatively complex, and each read and write has multiple control and waiting cycles. Therefore, in order to improve efficiency, the address increment fragmented read and write method is usually adopted, and it is not possible to read data at any address at any time like SRAM.
This solution adopts a completely dynamic memory allocation mechanism, that is, when each module requests, if it is not the same field data, it can be allocated a new memory, and once the data in the memory is no longer valid, the memory is released. In this way, each memory has its own attributes, marking whether it is in use or free memory, and whether the data in the current memory is in the queue waiting to be used, so the memory needs to be divided into 3 blocks. One block stores point-by-point correction parameters, one block stores current field data, and the other block stores the previous field data (that is, the data being sent). This requires that the data needs to be sent within a field synchronization cycle, and this requirement is completely achievable.
Bus scheduling is the core part of this module. It is necessary to accurately calculate the bus bandwidth usage and determine the depth of each FIFO to ensure that each FIFO will not overflow or read empty.
The bus scheduler needs to schedule 3 memory blocks, and also needs to maintain a starting address of an offset address and an offset address count register for each module. In order to facilitate the calculation of the offset address, two physical rows of SDRAM are used to store one row of data, and the excess part is left empty.
The arbitration algorithm of the bus scheduler is: the point-by-point correction parameters are the same as the priority of the corrected data written into the SDRAM, and the bus is occupied in a first-come-first-served manner. The bus occupation is triggered by the pointer of each FIFO. After a field of data is written into the SDRAM, it starts to be sent. It is necessary to read the data of the nth, n+ 128th, and n+ 256th rows in turn to the data transmission FIFO0, 1, and 2, and wait for the data transmission unit to start sending.

3.3 LCD interface and point-by-point correction
The LCD interface of PXA255 is configured as a smart panel. For the specific timing relationship, please refer to the manual of PXA255. According to these timing relationships, FPGA reads the data and performs the next processing.
Since the parameters of LED tubes cannot be completely consistent during the production process, LED tubes must be screened in order to obtain good image display effects. This is also an important reason why LED screens are expensive.
The point-by-point correction technology can adjust the brightness of LEDs point by point, and improve the consistency of the brightness of the display screen by an order of magnitude, so that the purchasing manufacturers can relax the requirements of LED brightness and color, and the cost of LED procurement is greatly reduced. In addition, the point-by-point correction technology used by the system can modify the correction parameters online, so that the correction parameters can also be modified after the LED screen is put into operation, compensating for the impact of LED tube aging on the display effect and increasing the service life of the LED screen. Therefore, the point-by-point correction technology makes LED modules an ideal solution as the basic components of indoor and outdoor full-color display screens.
The point-by-point correction parameters are stored in the SD card. After the system is powered on, ARM first transmits the data to the FPGA through the LCD interface (configured as GPIO at this time), and the FPGA stores it in the SDRAM. After that, the data input by the LCD interface can be corrected.

3.4 Data Transmission
When data is transmitted, each line of data is treated as a frame, and transmission begins after adding a specific frame header. In order to reduce the number of buses, a serial bus is used. Each group of signals has 4 channels, namely the source synchronous clock and the serial data of the three primary colors RGB. The signals are all transmitted in the form of LVDS (Low Voltage Differential Signal). LVDS transmits data in a differential manner, has a stronger common-mode noise suppression capability than single-ended transmission, and can achieve long-distance, high-speed and low-power transmission. Altera's Cyclone II series FPGA can easily obtain LVDS capabilities through I/O configuration.
The transmission frame header consists of a 4-byte synchronization header + current data row number + ID number. Since the correlation of continuous pixel values ​​of an image is relatively high, a pseudo-random code is used as the synchronization header, and its synchronization performance is relatively reliable. The current row number is used by the controller to determine whether a frame loss occurs, and to determine the storage address of the current data based on the current row number. Since each group of data is actually processed by two controllers separately (see Figure 1), a flag is required to intercept different data parts. The ID number is the standard for different controllers to intercept different numbers of columns in a row. When data is sent, the ID is zero. [page]

4 Full-color LED display controller
The full-color LED display controller is responsible for receiving, converting and processing the RGB three-primary color signals, and transmitting the signals to the LED display screen for display in a certain pattern and manner. The controller directly determines the display effect of the display screen, and also determines the performance of the LED display screen. The structure of the controller is shown in Figure 3.

Figure 3 Display controller structure block diagram
The architecture of the controller is similar to data distribution, and also adopts a secondary storage mode. It mainly includes four parts: data reception, Gamma correction and interleaving, scanning control output, bus scheduling and SDRAM control.
4.1 Memory allocation and bus scheduling
Since the data input field frequency and the LED scanning field frequency are usually not integer multiples, it may happen that the input of a field of data ends, and the processing result of the field data (after Gamma correction and interleaving) needs to be written to SDRAM, but at this time, the scanning of a field has not ended, that is, the area being read cannot be overwritten, and the data of the previous field has not been displayed and cannot be overwritten, so interleaved writing (that is, scanning reading) requires opening up three partitions.
The bus arbitration algorithm is: the control output module and the writing module adopt the first-come-first-served algorithm, while the reading and writing of the correction and interleaving process have the lowest priority and can be suspended when the previous two apply. Only when the current two no longer need the bus can they be allocated the right to use the bus.

4.2 Data Reception
In addition to synchronous judgment and serial-to-parallel conversion, the data receiving unit must also determine which data in a row needs to be processed by the controller. The controller intercepts the data of the 128×ID-128×(ID+1)-1 column in each row, and adds 1 to the ID number. The other data is output as is and sent to the next level controller. This control method is more flexible and reliable than the commonly used dip switch method.

4.3 Gamma correction and interleaving
Gamma correction can make the LED display effect closer to the physiological characteristics of the human eye, and because the PXA255 outputs 8-bit data, the system needs to correct it to 12 bits, which greatly improves the display contrast. Since the LED display controller adopts a bit-by-bit display method, the input data and the data output to the LED display are organized in different forms: the former is arranged by pixel points, while the latter is organized by different bits of pixel values.

4.4 The time for controlling the output
of 12-bit data display is (64, 32, 16, 8, 4, 2, 1, 1/2, 1/4, 1/8, 1/16, 1/32) * 128 * Tsclk, where Tsclk is the serial shift clock. After interleaving, the data display signals with different weights have different effective times, which can achieve the display effect.
The bus scheduler writes the interleaved data into the FIFO of this module. The control signal for reading the FIFO is generated by the module and counted. The number of shifts and weights need to be counted in the module to determine the effective time of issuing the latch signal and the display signal.

5 Conclusions
The experimental test results show that the system has appropriate brightness, fine resolution (64G colors), high field scanning frequency (about 400 Hz), and high pixels (320×240 dots), and can be used for outdoor broadcast-level applications. This design can adjust the brightness point by point, so that the purchasing manufacturer can relax the requirements of LED brightness and color, and the cost of LED procurement will also be reduced. The increase from 8 bits to 12 bits greatly increases the color level of the image, especially in low-brightness areas, which can perfectly reproduce the image, and Gamma correction makes the brightness change of the LED display more in line with the physiological characteristics of the human eye. In addition, in addition to receiving signals from ARM, it can also receive data signals from set-top boxes through the HDMI interface, which has broad market application prospects.