Phase locked loop CD4046 application

The meaning of phase locking is the automatic control of phase synchronization. An automatic control closed-loop system that can complete the phase synchronization of two electrical signals is called a phase locked loop, or PLL for short. It is widely used in technical fields such as broadcast communications, frequency synthesis, automatic control and clock synchronization. The phase locked loop mainly consists of a phase comparator (PC) and a voltage controlled oscillator (VCO). The low-pass filter consists of three parts, as shown in Figure 1.

figure 1

The output Uo of the voltage controlled oscillator is connected to an input end of the phase comparator, and the output frequency is determined by the average voltage Ud established on the low-pass filter. The external input signal Ui applied to the other input terminal of the phase comparator is compared with the output signal Uo from the voltage-controlled oscillator. The error output voltage UΨ generated by the comparison is proportional to the phase difference between the two signals Ui and Uo and is low-pass filtered. After filtering out the high-frequency components, an average voltage Ud is obtained. This average voltage Ud changes in the direction of reducing the difference between the VCO output frequency and the input frequency until the VCO output frequency and the input signal frequency are consistent. At this time, the frequencies of the two signals are the same, and the phase difference between the two signals remains constant (that is, synchronized), which is called phase locking.

figure 2

When the phase-locked loop is locked, it also has the ability to "capture" signals. The VCO can automatically track changes in the input signal within a certain range. If the input signal frequency changes within the capture range of the phase-locked loop, the phase-locked loop It can capture the input signal frequency and force the VCO to lock on this frequency. The application of phase-locked loop is very flexible. If the input signal frequency f1 is not equal to the VCO output signal frequency f2, and the two are required to maintain a certain relationship, such as a proportional relationship or a difference relationship, you can add an external arithmetic unit to meet different tasks. needs. In the past, phase-locked loops were mostly composed of discrete components and analog circuits. Nowadays, integrated circuit phase-locked loops are often used. CD4046 is a general-purpose CMOS phase-locked loop integrated circuit. It is characterized by a wide power supply voltage range (3V-18V) and an input It has high impedance (about 100MΩ) and low dynamic power consumption. When the center frequency f0 is 10kHz, the power consumption is only 600μW. It is a micro-power device. Figure 2 is the pin arrangement of CD4046, which adopts 16-pin dual in-line type. The functions of each pin are as follows:

The phase output terminal of pin 1 is high level when the loop is locked and low level when the loop is out of lock. Pin 2 is the output terminal of phase comparator I. Pin 3 is the comparison signal input terminal. 4-pin voltage controlled oscillator output. Pin 5 is the inhibit terminal, which is disabled when the level is high and allows the voltage-controlled oscillator to operate when the level is low. Pins 6 and 7 are connected to external oscillation capacitors. 8. The negative and positive terminals of the 16-pin power supply. The control end of the 9-pin voltage controlled oscillator. 10-pin demodulation output terminal, used for FM demodulation. Pins 11 and 12 are connected to external oscillation resistors. Pin 13 is the output terminal of phase comparator II. 14-pin signal input terminal. Pin 15 is the negative pole of the independent Zener voltage regulator tube inside.

image 3

Figure 3 is the internal electrical block diagram of CD4046, which mainly consists of phase comparison I and II, voltage controlled oscillator (VCO), linear amplifier, source follower, shaping circuit and other parts. Comparator I adopts an XOR gate structure. When the level states of the two input signals Ui and Uo are different (that is, one is high level and the other is low level), the output signal UΨ is high level; vice versa. , when the level status of Ui and Uo is the same (that is, both are high, or both are low), the UΨ output is low level. When the phase difference Δφ of Ui and Uo changes in the range of 0°-180°, the pulse width m of UΨ also changes accordingly, that is, the duty cycle also changes. It can be seen from the waveforms of the input and output signals of comparator I (as shown in Figure 4) that the frequency of its output signal is equal to twice the frequency of the input signal, and maintains a 90° phase shift with the center frequency between the two input signals. It can also be seen from the figure that fout is not necessarily a symmetrical waveform. For phase comparator I, it requires the duty cycle of Ui and Uo to be 50% (i.e. square wave), so that the locking range can be maximized.

Figure 4

Phase Comparator II is a digital storage network controlled by the rising edge of the signal. It has low requirements on the input signal duty cycle, allows input asymmetric waveforms, has a wide capture frequency range, and will not lock on the harmonics of the input signal. It provides two outputs: a digital error signal and a locking signal (phase pulse). When locking is achieved, a 0° phase shift is maintained between the two input signals of phase comparator II.

For phase comparator II, when the input signal at pin 14 is lower in frequency than the comparison signal at pin 3, the output is logic "0"; otherwise, the output is logic "1". If the frequency of the two signals is the same but the phase is different, when the phase of the input signal lags behind the comparison signal, the phase comparator II outputs a positive pulse, and when the phase leads, the output is a negative pulse. In both cases, a negative pulse with the same width as the above-mentioned positive and negative pulses is generated from pin 1. The width of the positive and negative pulses output from phase comparator II is equal to the phase difference between the rising edges of the two input pulses. When the frequency and phase of the two input pulses are the same, the output of the phase comparator II is in a high impedance state, and pin 1 outputs a high level. The above waveform is shown in Figure 5. It can be seen that the status of the two input signals can be judged from whether the output signal of pin 1 is a negative pulse or a fixed high level.

 Figure 5

The CD4046 phase-locked loop uses an RC-type voltage-controlled oscillator, and must be connected to an external capacitor C1 and resistor R1 as charging and discharging components. When the PLL has requirements for the frequency width of the input signal to be tracked, an external resistor R2 is also required. Since the VCO is a current-controlled oscillator, the charging current of the timing capacitor C1 is proportional to the control voltage input from pin 9, so that the oscillation frequency of the VCO is also proportional to the control voltage. When the VCO control voltage is 0, its output frequency is the lowest; when the input control voltage is equal to the power supply voltage VDD, the output frequency increases linearly to the highest output frequency. The range of VCO oscillation frequency is determined by R1, R2 and C1. Since its charging and discharging are completed by the same capacitor C1, its output waveform is a symmetrical square wave. Generally, the maximum frequency of CD4046 is 1.2MHz (VDD=15V). If VDD<15V, fmax should be lowered.

There is also a linear amplifier and shaping circuit inside CD4046, which can convert the weak input signal of about 100mV from pin 14 into a square wave or pulse signal and send it to the two-phase comparator. The source tracker is an amplifier with a gain of 1. The output voltage of the VCO passes through the source tracker to pin 10 for FM demodulation. The Zener diode can be used alone, and its voltage regulation value is 5V. If matched with a TTL circuit, it can be used as an auxiliary power supply.

To sum up, the working principle of CD4046 is as follows: after the input signal Ui is input from pin 14, it is amplified and shaped by amplifier A1 and then added to the input terminals of phase comparators I and II. In Figure 3, switch K is turned to pin 2, then the comparison Device I performs phase comparison between the comparison signal Uo input from pin 3 and the input signal Ui, and the error voltage UΨ output from the phase comparator reflects the phase difference between the two. After UΨ is filtered by R3, R4 and C2, a control voltage Ud is obtained and applied to the input terminal 9 of the voltage controlled oscillator VCO to adjust the oscillation frequency f2 of the VCO so that f2 quickly approaches the signal frequency f1. The output of the VCO goes through the divider and then enters the phase comparator I, and continues the phase comparison with Ui. Finally, f2 = f1, and the phase difference between the two is a certain value, achieving phase locking. If the switch K is set to pin 13, the phase comparator II will work. The process is the same as above and will not be described again.