Design of large LED dot matrix display system based on ARM

Large-scale LED display system is an electronic advertising media formed with the rapid development of computer and related microelectronics and optoelectronics technology. It uses dot matrix modules or pixel units composed of light-emitting diodes to form a large-area display screen, which is mainly used to display characters, images and other information. It adopts low-voltage scanning drive and has the advantages of low power consumption, long life, low cost, high brightness, few failures, large viewing angle, and long visual distance. With the improvement of LED material technology and process, large-scale LED display system has become one of the mainstream products of flat panel display with outstanding advantages. It is widely used in occasions such as securities trading, airport flights, ports, stations, etc., and is widely used in the field of information display.

1 System structure and principle

Large-scale LED display system is generally divided into two parts: display driver module and main control board.

1.1 Display module

Large-scale LED display system uses the characteristics of human vision to adopt row-by-row scanning and column driving to save hardware expenses. This system adopts 1/16 row-by-row scanning, so the entire display screen is divided into 16 rows of the same name. The schematic diagram of the display module is shown in Figure 1.

Schematic diagram of display module

Figure 1 Schematic diagram of display module

Each display module is a 64 × 32 small dot matrix screen, divided into two parts, 16 rows each, and each part has 8 groups of column data latches. The upper and lower parts reuse a 4-16 decoder U3, which is driven to scan 1/16 row by row, and 16 groups of column drive latches are required to latch the column display data. When the parallel bus data transmission method is adopted, a 4-16 decoder U2 is required to enable the column latch. When the dot matrix data is refreshed, two-level latches are required to latch the column display data, otherwise the display tail phenomenon will appear. The data being displayed this time is stored in the second-level latch. The main control board refreshes the column data of the next row of data to be displayed by the first-level latch on the screen. After the data to be displayed in the next row is transmitted, it is latched to the second-level latch output and the next row of display is driven. Under the parallel bus method, the second-level latch is still more economical than the scheme of serial data transmission and then converted to parallel output.

When display modules are horizontally cascaded, the idea of ​​staggered cascading is used to make it versatile and embeddable. The strobe line will be staggered once at each level and passed to the next level, always making the first strobe line BLK_EN0 the enable control line of the first-level column latch decoder. N strobe lines can sequentially select n-level horizontal cascade modules, so that the same display modules can be used to arbitrarily combine into horizontal cascade strip screens.

Using the idea of ​​staggered cascading, the decoder U2 of the first-level latch on the horizontally cascaded display module can be selected in turn, and the decoder can select the first-level column data latch in turn, so that the first-level column data latch on the horizontally cascaded screen can be regarded as a continuous storage unit, which is the basis for using DMA parallel data transmission control. [page]

1.2 Interface design between main control circuit and LED screen

This display system uses S3C44B0X based on ARM7TDM I core with internal DMA controller as the main controller, making it work in ARM state and using 16-bit bus. Since the LED screen is virtually regarded as a continuous storage unit, the address space 0x2000000~0x4000000 is allocated to it.

The schematic diagram of the main control board and LED screen interface circuit is shown in Figure 2.

The structure of a large LED display screen can be divided into vertical cascade and horizontal cascade, which is similar to a three-dimensional array. Assume a three-dimensional array LED [i] [j] [k], where:

i = 0, 1, 2, ..., m represents the serial number of the vertical cascade level of the LED screen.

j = 0, 1, 2, ..., n represents the serial number of the horizontal cascade level of the LED screen.

k = 0, 1, 2, ..., 16 represents the serial number of the 16 first-level column data latches on the display module.

Since the system uses a 16-bit parallel bus data transmission method and regards the LED screen as a continuous storage unit, A [4∶1] is used

as the decoding input of the first-level column data latch decoder (U2 in Figure 1) on the display module, which is the k variable of the three-dimensional array; A [8∶5] is used as the decoding input of the decoder (U14 in Figure 2) for selecting the horizontal cascade display module, which is the j variable of the three-dimensional array; since the LED screen must have good flexibility and the technical requirements of the dot matrix code storage order required by DMA data transmission, the vertical cascade level selection does not meet the conditions for using the address bus decoding selection, so S3C44B0X's PG [2∶0] is used as the decoding input of the vertical cascade level selection decoder, which is the i variable of the three-dimensional array.

Schematic diagram of the interface circuit between the main control board and the LED display screen

Figure 2 Schematic diagram of the interface circuit between the main control board and the LED display screen. [page]

Since the states on the address and data buses are constantly changing, the address and data signals should be latched when writing to the LED screen. U2, U3 and U4 are used on the main control board to latch the states of the address and data buses when writing to the LED. The LED screen is assigned the first address of 0x2000000. When writing to it, the nGCSl and nWE pins of S3C44B0X will appear an effective low level with a programmable control delay. nGCSl is used as the latch enable control signal of U2, U3 and U4 through a NOT gate to ensure that the signals on the address and data buses are latched only when the LED screen is accessed. nWE is used as the latch enable control signal of the first-level column data latch (U4~U19 in Figure 1) at the screen end through a NOT gate to ensure that the refresh data is latched only when it appears stably at the input end of the column data latch. PC I0 of S3C44B0X is used as the latch enable control signal line of all the second-level latches (U20~U35 in Figure 1) at the screen end; PC [3∶0] of S3C44BOX is used as the decoding input of the 16-row driver decoder (U3 in Figure 1). Since the main control board only needs to control the output of the LED screen during data transmission, and no signal feedback is required, the interface circuit adopts a cheap 5V powered HCT circuit chip solution to meet the logic level conversion from the main control chip 313V to the LED screen 5V.

When DMA transmits data, the DMA write operation is more concerned, and the timing is shown in Figure 3. At t1, the DMA write operation starts, and the address and refresh data of the corresponding position of the LED screen appear on the address and data bus; at t2, the nGCS1 pin appears an effective low level, and the data on the address and data bus is latched into U2~U4 and output; at t3, the nWE pin appears an effective low level, and the output data of U2~U4 is latched into the first-level column data latch at the screen end and output. In this way, the main controller completes a column data refresh.

DMA write operation timing diagram

Figure 3 DMA write operation timing diagram.

2 Software Design

2.1 LED screen display program design

Since the internal DMA controller of S3C44B0X is used for data transmission and control, the display program is greatly simplified, and the program flow is shown in Figure 4. The transmission of the dot matrix code is completed by the DMA controller. Before starting the DMA data transmission, you only need to assign the first address of the dot matrix code, the first address of the LED screen and the value of the transmission data volume to the corresponding control word, and then start the DMA operation. After completing the transmission of all the dot matrix codes of the same name row, the refreshed data is latched to the second-level column data latch output, and the same name row is driven to display. In this way, after 16 rows of the same name are displayed in a loop, a frame of dot matrix display is completed. [page]

Display program flow chart

Figure 4 Display program flow chart.

2.2 Dot matrix sorting

Due to the circuit structure of the LED display module and the use of 16-bit parallel bus and DMA data transmission technology, the order of dot matrix code during display needs to meet the following requirements:

(1) The 16-bit parallel bus transmits data once, that is, a DMA write operation transmits two bytes of dot matrix code, and the low-order and high-order bytes are respectively transmitted to the same-name row and column data latches of two adjacent vertical cascade modules. Therefore, the same-name row and column dot matrix codes of adjacent vertical cascade modules should be stored continuously.

(2) Due to the decoding selection circuit structure of the first-level column data latch of the display module and the DMA data transmission requirements, the same-name row dot matrix of the upper and lower parts of the same display module should be stored continuously in sequence according to the selection order of the column data latch.

(3) The dot matrix code of a series of horizontal cascade levels of two adjacent vertical cascade levels should be sorted according to the principles of (1) and (2).

(4) Each vertical cascade level is sequentially sorted according to the principles of (1), (2), and (3).

(5) In the 16-line scanning display mode, a large LED screen is divided into 16 rows of the same name, and each row of the same name is sorted according to the principles of (1), (2), (3), and (4).

Taking the data sorting of the first row of the same name row of a 128 × 64 dot matrix screen as an example, as shown in Figure 5, the storage order of the dot matrix code of the first row of the same name row should be: a, b, ... z, A, B, ... Z, ....

128 × 64 dot matrix screen first row of the same name row data sorting diagram

Figure 5 128 × 64 dot matrix screen first row of the same name row data sorting diagram.

3 Conclusions

The use of parallel bus DMA data transmission technology simplifies the software and hardware design of the LED display system, reduces the system cost, and achieves good display quality. Under the system clock of 2211184MHz, the display frame rate of 512 × 256 (8m2) monochrome dot matrix screen reaches 250Hz, and 1 byte is transmitted in an average of 120ns, achieving the purpose of using a single CPU system instead of a multi-machine system to control the LED display system. However, in order to make the previous generation of display driver boards still usable, the dot matrix code needs to be sorted, and the display can only be displayed in page mode, so a large-capacity memory is required for multi-page dynamic scrolling display. For a 512 × 256 monochrome dot matrix screen, a capacity of tens of megabytes is required. The use of 32-bit ARM7TDMl core advanced controller S3C44B0X and cheap large-capacity SDRAM memory can solve this problem well. If a display driver board designed for DMA control display is used, the dot matrix code does not need to be sorted, and a SRAM of hundreds of KB can meet the system requirements.